| Age | Commit message (Expand) | Author |
| 2020-07-17 | CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394) | LDj3SNuD |
| 2020-07-17 | CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390) | LDj3SNuD |
| 2020-07-13 | Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335) | LDj3SNuD |
| 2020-07-13 | Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli vari... | riperiperi |
| 2020-06-24 | Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303) | riperiperi |
| 2020-06-16 | Add Profiled Persistent Translation Cache. (#769) | LDj3SNuD |
| 2020-05-27 | Add FMaxNmV & FMinNmV Inst.s with Test. (#1279) | LDj3SNuD |
| 2020-05-04 | Implement a new physical memory manager and replace DeviceMemory (#856) | gdkchan |
| 2020-04-17 | Improve V128 (#1097) | Ficture Seven |
| 2020-03-24 | Add Fcvtas_S/V & Fcvtau_S/V. (#1018) | LDj3SNuD |
| 2020-03-14 | Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982) | riperiperi |
| 2020-03-11 | Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other... | gdkchan |
| 2020-03-10 | Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960) | gdkchan |
| 2020-03-01 | Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954) | gdkchan |
| 2020-03-01 | Implement FACGE and FACGT (Scalar and Vector) AArch64 SIMD instructions (#956) | gdkchan |
| 2020-02-24 | Add most of the A32 instruction set to ARMeilleure (#897) | riperiperi |
| 2019-12-29 | Implemented fast paths for: (#846) | LDj3SNuD |
| 2019-11-14 | Add Mrs & Msr (Nzcv) Inst., with Tests. (#819) | LDj3SNuD |
| 2019-10-24 | Add Sli_S/V & Sri_S/V inst.s (fast & slow paths), with Tests. (#797) | LDj3SNuD |
| 2019-10-04 | Add Tbx Inst. (fast & slow paths), with Tests. (#782) | LDj3SNuD |
| 2019-08-08 | Add a new JIT compiler for CPU code (#693) | gdkchan |
| 2019-07-08 | Add Saddlv_V Inst. Improve Cnt_V, Dup_Gp & Ins_Gp Tests. Tuneup Cls_V & Clz_V... | LDj3SNuD |
| 2019-06-29 | Implement the remaining tests for Simd and Fp instructions of data processing... | LDj3SNuD |
| 2019-06-12 | Implement a custom value generator for the Tests of the CLS and CLZ instructi... | LDj3SNuD |
| 2019-05-30 | Add FCVT <Hd>, <Sn> and FCVT <Sd>, <Hn> Inst.; add Tests. (#692) | LDj3SNuD |
| 2019-05-29 | Add Smaxv_V, Sminv_V, Umaxv_V, Uminv_V Inst.; add Tests. (#691) | LDj3SNuD |
| 2019-04-26 | Sse optimized the Scalar & Vector fp-to-fp conversion instructions (MNPZ & IX... | LDj3SNuD |
| 2019-04-20 | Sse optimized the 32-bit Vector & Scalar integer-to-fp conversion instruction... | LDj3SNuD |
| 2019-04-12 | Sse optimized the Vector & Scalar fp-to-integer conversion instructions (unsi... | LDj3SNuD |
| 2019-04-03 | Sse optimized all the fp to integer conversion instructions (signed) with Tes... | LDj3SNuD |
| 2019-03-23 | Add Tbl_V Sse opt. with Tests. (#651) | LDj3SNuD |
| 2019-03-13 | Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. ... | LDj3SNuD |
| 2019-03-01 | Create CpuTestSimdImm.cs (#608) | LDj3SNuD |
| 2019-02-23 | Add Tests for instructions Fcvtzs_Gp_Fixed & Fcvtzu_Gp_Fixed, Scvtf_Gp_Fixed ... | LDj3SNuD |
| 2019-02-18 | Update CpuTestMisc.cs | LDj3SNuD |
| 2019-02-04 | Implement speculative translation on the CPU (#515) | gdkchan |
| 2019-01-29 | Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tes... | LDj3SNuD |
| 2018-12-26 | Fix Frecpe_S/V and Frsqrte_S/V (full FP emu.). Add Sse Opt. & SoftFloat Impl.... | LDj3SNuD |
| 2018-12-17 | Add Frintz_S/V opcode and unit test, correction of some unit tests (#523) | MS-DOS1999 |
| 2018-12-01 | Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516) | LDj3SNuD |
| 2018-11-18 | Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V... | LDj3SNuD |
| 2018-11-01 | Add Flush-to-zero mode (input, output) to FP instructions (slow paths); updat... | LDj3SNuD |
| 2018-10-30 | Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) | Alex Barney |
| 2018-10-28 | Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 ... | LDj3SNuD |
| 2018-10-23 | Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. ... | LDj3SNuD |
| 2018-10-17 | Remove unnecessary usings (#463) | gdkchan |
| 2018-10-13 | Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_... | LDj3SNuD |
| 2018-10-05 | Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437) | LDj3SNuD |
| 2018-09-17 | Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; a... | LDj3SNuD |
| 2018-09-08 | Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407) | LDj3SNuD |