Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Superseded.

* Update AInstEmitSimdCvt.cs

* Update ASoftFloat.cs

* Nit.

* Update PackageReferences.

* Update AInstEmitSimdArithmetic.cs

* Update AVectorHelper.cs

* Update ASoftFloat.cs

* Update ASoftFallback.cs

* Update AThreadState.cs

* Create FPType.cs

* Create FPExc.cs

* Create FPCR.cs

* Create FPSR.cs

* Update ARoundMode.cs

* Update APState.cs

* Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover.

* Nits.

3 files changed, 208 insertions, 44 deletions

diff --git a/Ryujinx.Tests/Cpu/CpuTest.cs b/Ryujinx.Tests/Cpu/CpuTest.cs
index 24585fe7..4587189b 100644
--- a/Ryujinx.Tests/Cpu/CpuTest.cs
+++ b/Ryujinx.Tests/Cpu/CpuTest.cs
@@ -178,11 +178,30 @@ namespace Ryujinx.Tests.Cpu
             return GetThreadState();
         }
 
+        /// <summary>Rounding Mode control field.</summary>
+        public enum RMode
+        {
+            /// <summary>Round to Nearest (RN) mode.</summary>
+            RN,
+            /// <summary>Round towards Plus Infinity (RP) mode.</summary>
+            RP,
+            /// <summary>Round towards Minus Infinity (RM) mode.</summary>
+            RM,
+            /// <summary>Round towards Zero (RZ) mode.</summary>
+            RZ
+        };
+
         /// <summary>Floating-point Control Register.</summary>
         protected enum FPCR
         {
+            /// <summary>Rounding Mode control field.</summary>
+            RMode = 22,
+            /// <summary>Flush-to-zero mode control bit.</summary>
+            FZ    = 24,
             /// <summary>Default NaN mode control bit.</summary>
-            DN = 25
+            DN    = 25,
+            /// <summary>Alternative half-precision control bit.</summary>
+            AHP   = 26
         }
 
         /// <summary>Floating-point Status Register.</summary>
@@ -514,6 +533,27 @@ namespace Ryujinx.Tests.Cpu
             return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), (byte)1);
         }
 
+        protected static ushort GenNormal_H()
+        {
+            uint Rnd;
+
+            do       Rnd = TestContext.CurrentContext.Random.NextUShort();
+            while (( Rnd & 0x7C00u) == 0u ||
+                   (~Rnd & 0x7C00u) == 0u);
+
+            return (ushort)Rnd;
+        }
+
+        protected static ushort GenSubnormal_H()
+        {
+            uint Rnd;
+
+            do      Rnd = TestContext.CurrentContext.Random.NextUShort();
+            while ((Rnd & 0x03FFu) == 0u);
+
+            return (ushort)(Rnd & 0x83FFu);
+        }
+
         protected static uint GenNormal_S()
         {
             uint Rnd;
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
index 279f9f0c..795d649a 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
@@ -79,6 +79,47 @@ namespace Ryujinx.Tests.Cpu
                                  0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
         }
 
+        private static IEnumerable<ulong> _4H_F_()
+        {
+            yield return 0xFBFFFBFFFBFFFBFFul; // -Max Normal
+            yield return 0x8400840084008400ul; // -Min Normal
+            yield return 0x83FF83FF83FF83FFul; // -Max Subnormal
+            yield return 0x8001800180018001ul; // -Min Subnormal
+            yield return 0x7BFF7BFF7BFF7BFFul; // +Max Normal
+            yield return 0x0400040004000400ul; // +Min Normal
+            yield return 0x03FF03FF03FF03FFul; // +Max Subnormal
+            yield return 0x0001000100010001ul; // +Min Subnormal
+
+            if (!NoZeros)
+            {
+                yield return 0x8000800080008000ul; // -Zero
+                yield return 0x0000000000000000ul; // +Zero
+            }
+
+            if (!NoInfs)
+            {
+                yield return 0xFC00FC00FC00FC00ul; // -Infinity
+                yield return 0x7C007C007C007C00ul; // +Infinity
+            }
+
+            if (!NoNaNs)
+            {
+                yield return 0xFE00FE00FE00FE00ul; // -QNaN (all zeros payload)
+                yield return 0xFDFFFDFFFDFFFDFFul; // -SNaN (all ones  payload)
+                yield return 0x7E007E007E007E00ul; // +QNaN (all zeros payload) (DefaultNaN)
+                yield return 0x7DFF7DFF7DFF7DFFul; // +SNaN (all ones  payload)
+            }
+
+            for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
+            {
+                uint Rnd1 = (uint)GenNormal_H();
+                uint Rnd2 = (uint)GenSubnormal_H();
+
+                yield return (Rnd1 << 48) | (Rnd1 << 32) | (Rnd1 << 16) | Rnd1;
+                yield return (Rnd2 << 48) | (Rnd2 << 32) | (Rnd2 << 16) | Rnd2;
+            }
+        }
+
         private static IEnumerable<ulong> _1S_F_()
         {
             yield return 0x00000000FF7FFFFFul; // -Max Normal    (float.MinValue)
@@ -265,6 +306,38 @@ namespace Ryujinx.Tests.Cpu
             };
         }
 
+        private static uint[] _F_Cvtl_V_4H4S_8H4S_()
+        {
+            return new uint[]
+            {
+                0x0E217800u // FCVTL V0.4S, V0.4H
+            };
+        }
+
+        private static uint[] _F_Cvtl_V_2S2D_4S2D_()
+        {
+            return new uint[]
+            {
+                0x0E617800u // FCVTL V0.2D, V0.2S
+            };
+        }
+
+        private static uint[] _F_Cvtn_V_4S4H_4S8H_()
+        {
+            return new uint[]
+            {
+                0x0E216800u // FCVTN V0.4H, V0.4S
+            };
+        }
+
+        private static uint[] _F_Cvtn_V_2D2S_2D4S_()
+        {
+            return new uint[]
+            {
+                0x0E616800u // FCVTN V0.2S, V0.2D
+            };
+        }
+
         private static uint[] _F_Recpx_Sqrt_S_S_()
         {
             return new uint[]
@@ -890,6 +963,100 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Pairwise] [Explicit]
+        public void F_Cvtl_V_4H4S_8H4S([ValueSource("_F_Cvtl_V_4H4S_8H4S_")] uint Opcodes,
+                                       [Values(0u)]     uint Rd,
+                                       [Values(1u, 0u)] uint Rn,
+                                       [ValueSource("_4H_F_")] ulong Z,
+                                       [ValueSource("_4H_F_")] ulong A,
+                                       [Values(0b0u, 0b1u)] uint Q, // <4H, 8H>
+                                       [Values(RMode.RN)] RMode RMode)
+        {
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= ((Q & 1) << 30);
+
+            Vector128<float> V0 = MakeVectorE0E1(Q == 0u ? Z : 0ul, Q == 1u ? Z : 0ul);
+            Vector128<float> V1 = MakeVectorE0E1(Q == 0u ? A : 0ul, Q == 1u ? A : 0ul);
+
+            int Rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int Fpcr = (int)RMode << (int)FPCR.RMode;
+            Fpcr |= Rnd & (1 << (int)FPCR.FZ);
+            Fpcr |= Rnd & (1 << (int)FPCR.DN);
+            Fpcr |= Rnd & (1 << (int)FPCR.AHP);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, Fpcr: Fpcr);
+
+            CompareAgainstUnicorn(FpsrMask: FPSR.IOC | FPSR.OFC | FPSR.UFC | FPSR.IXC);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Cvtl_V_2S2D_4S2D([ValueSource("_F_Cvtl_V_2S2D_4S2D_")] uint Opcodes,
+                                       [Values(0u)]     uint Rd,
+                                       [Values(1u, 0u)] uint Rn,
+                                       [ValueSource("_2S_F_")] ulong Z,
+                                       [ValueSource("_2S_F_")] ulong A,
+                                       [Values(0b0u, 0b1u)] uint Q, // <2S, 4S>
+                                       [Values(RMode.RN)] RMode RMode)
+        {
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= ((Q & 1) << 30);
+
+            Vector128<float> V0 = MakeVectorE0E1(Q == 0u ? Z : 0ul, Q == 1u ? Z : 0ul);
+            Vector128<float> V1 = MakeVectorE0E1(Q == 0u ? A : 0ul, Q == 1u ? A : 0ul);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Cvtn_V_4S4H_4S8H([ValueSource("_F_Cvtn_V_4S4H_4S8H_")] uint Opcodes,
+                                       [Values(0u)]     uint Rd,
+                                       [Values(1u, 0u)] uint Rn,
+                                       [ValueSource("_2S_F_")] ulong Z,
+                                       [ValueSource("_2S_F_")] ulong A,
+                                       [Values(0b0u, 0b1u)] uint Q, // <4H, 8H>
+                                       [Values(RMode.RN)] RMode RMode) // Unicorn seems to default all rounding modes to RMode.RN.
+        {
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= ((Q & 1) << 30);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+
+            int Rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int Fpcr = (int)RMode << (int)FPCR.RMode;
+            Fpcr |= Rnd & (1 << (int)FPCR.FZ);
+            Fpcr |= Rnd & (1 << (int)FPCR.DN);
+            Fpcr |= Rnd & (1 << (int)FPCR.AHP);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, Fpcr: Fpcr);
+
+            CompareAgainstUnicorn(FpsrMask: FPSR.IOC | FPSR.OFC | FPSR.UFC | FPSR.IXC | FPSR.IDC);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Cvtn_V_2D2S_2D4S([ValueSource("_F_Cvtn_V_2D2S_2D4S_")] uint Opcodes,
+                                       [Values(0u)]     uint Rd,
+                                       [Values(1u, 0u)] uint Rn,
+                                       [ValueSource("_1D_F_")] ulong Z,
+                                       [ValueSource("_1D_F_")] ulong A,
+                                       [Values(0b0u, 0b1u)] uint Q, // <2S, 4S>
+                                       [Values(RMode.RN)] RMode RMode) // Unicorn seems to default all rounding modes to RMode.RN.
+        {
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= ((Q & 1) << 30);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise] [Explicit]
         public void F_Recpx_Sqrt_S_S([ValueSource("_F_Recpx_Sqrt_S_S_")] uint Opcodes,
                                      [ValueSource("_1S_F_")] ulong A)
         {
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs b/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs
deleted file mode 100644
index 3c8ad071..00000000
--- a/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs
+++ /dev/null
@@ -1,43 +0,0 @@
-using ChocolArm64.State;
-
-using NUnit.Framework;
-
-using System.Runtime.Intrinsics;
-using System.Runtime.Intrinsics.X86;
-
-namespace Ryujinx.Tests.Cpu
-{
-    public class CpuTestSimdCvt : CpuTest
-    {
-        [TestCase((ushort)0x0000, 0x00000000u)] // Positive Zero
-        [TestCase((ushort)0x8000, 0x80000000u)] // Negative Zero
-        [TestCase((ushort)0x3E00, 0x3FC00000u)] // +1.5
-        [TestCase((ushort)0xBE00, 0xBFC00000u)] // -1.5
-        [TestCase((ushort)0xFFFF, 0xFFFFE000u)] // -QNaN
-        [TestCase((ushort)0x7C00, 0x7F800000u)] // +Inf
-        [TestCase((ushort)0x3C00, 0x3F800000u)] // 1.0
-        [TestCase((ushort)0x3C01, 0x3F802000u)] // 1.0009765625
-        [TestCase((ushort)0xC000, 0xC0000000u)] // -2.0
-        [TestCase((ushort)0x7BFF, 0x477FE000u)] // 65504.0 (Largest Normal)
-        [TestCase((ushort)0x03FF, 0x387FC000u)] // 0.00006097555 (Largest Subnormal)
-        [TestCase((ushort)0x0001, 0x33800000u)] // 5.96046448e-8 (Smallest Subnormal)
-        public void Fcvtl_V_f16(ushort Value, uint Result)
-        {
-            uint Opcode = 0x0E217801; // FCVTL V1.4S, V0.4H
-
-            Vector128<float> V0 = Sse.StaticCast<ushort, float>(Sse2.SetAllVector128(Value));
-
-            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0);
-
-            Assert.Multiple(() =>
-            {
-                Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V1), (byte)0), Is.EqualTo(Result));
-                Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V1), (byte)1), Is.EqualTo(Result));
-                Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V1), (byte)2), Is.EqualTo(Result));
-                Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V1), (byte)3), Is.EqualTo(Result));
-            });
-
-            CompareAgainstUnicorn();
-        }
-    }
-}