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authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2019-03-13 09:23:52 +0100
committerjduncanator <1518948+jduncanator@users.noreply.github.com>2019-03-13 19:23:52 +1100
commit1bef70c068f8aeb6a3a518b8ca635de19122da14 (patch)
tree84d3ead95523f4803de1e6288f38ad45d6039005 /Ryujinx.Tests/Cpu
parenta0aecd1ff85437890bb6a86fcc71fc90e80a4d24 (diff)
Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614)
* Update CountLeadingZeros(). * Remove obsolete Tests. * Follow-up. * Follow-up. * Follow-up. * Add Mla_V, Mls_V & Mul_V Tests. * Update PackageReferences. * Remove EmitLd/Stvectmp2(). * Remove Dup. Nits. * Remove EmitLd/Stvectmp2() & Dup; nits. * Remove Tmp stuff & Dup; rework Fcvtz() as Fcvtn(). * Remove Tmp stuff, EmitLd/Stvectmp2() & Dup. Nits. * Add (R)shrn_V Sse opt.; add "Part" & "Shift" opt.. Remove Tmp stuff; remove Dup. Nits. * Add Mla/Mls/Mul_V Sse opt.. Add "Part" opt.. Remove EmitLd/Stvectmp2(), remove Dup. Nits. * Nits. * Nits. * Nit. * Add "Part" opt.. Nit. * Nit. * Nit. * Add Cmhi_V & Cmhs_V Sse opt..
Diffstat (limited to 'Ryujinx.Tests/Cpu')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs34
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdExt.cs7
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdIns.cs11
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdReg.cs64
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs47
5 files changed, 98 insertions, 65 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
index 2f8604eb..63e0bda8 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
@@ -8,26 +8,6 @@ namespace Ryujinx.Tests.Cpu
{
public class CpuTestSimdArithmetic : CpuTest
{
- [TestCase(0x00000000u, 0x7F800000u)]
- [TestCase(0x80000000u, 0xFF800000u)]
- [TestCase(0x00FFF000u, 0x7E000000u)]
- [TestCase(0x41200000u, 0x3DCC8000u)]
- [TestCase(0xC1200000u, 0xBDCC8000u)]
- [TestCase(0x001FFFFFu, 0x7F800000u)]
- [TestCase(0x007FF000u, 0x7E800000u)]
- public void Frecpe_S(uint a, uint result)
- {
- uint opcode = 0x5EA1D820; // FRECPE S0, S1
-
- Vector128<float> v1 = MakeVectorE0(a);
-
- CpuThreadState threadState = SingleOpcode(opcode, v1: v1);
-
- Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(result));
-
- CompareAgainstUnicorn();
- }
-
[TestCase(0x3FE66666u, false, 0x40000000u)]
[TestCase(0x3F99999Au, false, 0x3F800000u)]
[TestCase(0x404CCCCDu, false, 0x40400000u)]
@@ -601,19 +581,5 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
-
- [TestCase(0x41200000u, 0x3EA18000u)]
- public void Frsqrte_S(uint a, uint result)
- {
- uint opcode = 0x7EA1D820; // FRSQRTE S0, S1
-
- Vector128<float> v1 = MakeVectorE0(a);
-
- CpuThreadState threadState = SingleOpcode(opcode, v1: v1);
-
- Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(result));
-
- CompareAgainstUnicorn();
- }
}
}
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs b/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs
index f232989f..b8548169 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs
@@ -19,7 +19,8 @@ namespace Ryujinx.Tests.Cpu
}
#endregion
- private const int RndCnt = 2;
+ private const int RndCnt = 2;
+ private const int RndCntIndex = 2;
[Test, Pairwise, Description("EXT <Vd>.8B, <Vn>.8B, <Vm>.8B, #<index>")]
public void Ext_V_8B([Values(0u)] uint rd,
@@ -28,7 +29,7 @@ namespace Ryujinx.Tests.Cpu
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
[ValueSource("_8B_")] [Random(RndCnt)] ulong b,
- [Range(0u, 7u)] uint index)
+ [Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
{
uint imm4 = index & 0x7u;
@@ -52,7 +53,7 @@ namespace Ryujinx.Tests.Cpu
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
[ValueSource("_8B_")] [Random(RndCnt)] ulong b,
- [Range(0u, 15u)] uint index)
+ [Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
{
uint imm4 = index & 0xFu;
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs b/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
index 4ca54a2b..fe93f06e 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
@@ -67,7 +67,8 @@ namespace Ryujinx.Tests.Cpu
}
#endregion
- private const int RndCnt = 2;
+ private const int RndCnt = 2;
+ private const int RndCntIndex = 2;
[Test, Pairwise, Description("DUP <Vd>.<T>, <R><n>")]
public void Dup_Gp_W([Values(0u)] uint rd,
@@ -109,7 +110,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("DUP B0, V1.B[<index>]")]
public void Dup_S_B([ValueSource("_8B_")] [Random(RndCnt)] ulong a,
- [Range(0u, 15u)] uint index)
+ [Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
{
const int size = 0;
@@ -129,7 +130,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("DUP H0, V1.H[<index>]")]
public void Dup_S_H([ValueSource("_4H_")] [Random(RndCnt)] ulong a,
- [Range(0u, 7u)] uint index)
+ [Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
{
const int size = 1;
@@ -192,7 +193,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
- [Range(0u, 15u)] uint index,
+ [Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index,
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
{
const int size = 0;
@@ -217,7 +218,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
- [Range(0u, 7u)] uint index,
+ [Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
{
const int size = 1;
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
index 8d2f4e9a..1c418341 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
@@ -434,6 +434,26 @@ namespace Ryujinx.Tests.Cpu
};
}
+ private static uint[] _Mla_Mls_Mul_V_8B_4H_2S_()
+ {
+ return new uint[]
+ {
+ 0x0E209400u, // MLA V0.8B, V0.8B, V0.8B
+ 0x2E209400u, // MLS V0.8B, V0.8B, V0.8B
+ 0x0E209C00u // MUL V0.8B, V0.8B, V0.8B
+ };
+ }
+
+ private static uint[] _Mla_Mls_Mul_V_16B_8H_4S_()
+ {
+ return new uint[]
+ {
+ 0x4E209400u, // MLA V0.16B, V0.16B, V0.16B
+ 0x6E209400u, // MLS V0.16B, V0.16B, V0.16B
+ 0x4E209C00u // MUL V0.16B, V0.16B, V0.16B
+ };
+ }
+
private static uint[] _Sha1c_Sha1m_Sha1p_Sha1su0_V_()
{
return new uint[]
@@ -1786,6 +1806,50 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsD);
}
+ [Test, Pairwise]
+ public void Mla_Mls_Mul_V_8B_4H_2S([ValueSource("_Mla_Mls_Mul_V_8B_4H_2S_")] uint opcodes,
+ [Values(0u)] uint rd,
+ [Values(1u, 0u)] uint rn,
+ [Values(2u, 0u)] uint rm,
+ [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
+ [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong a,
+ [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong b,
+ [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+ {
+ opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
+ opcodes |= ((size & 3) << 22);
+
+ Vector128<float> v0 = MakeVectorE0E1(z, z);
+ Vector128<float> v1 = MakeVectorE0(a);
+ Vector128<float> v2 = MakeVectorE0(b);
+
+ SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
+
+ CompareAgainstUnicorn();
+ }
+
+ [Test, Pairwise]
+ public void Mla_Mls_Mul_V_16B_8H_4S([ValueSource("_Mla_Mls_Mul_V_16B_8H_4S_")] uint opcodes,
+ [Values(0u)] uint rd,
+ [Values(1u, 0u)] uint rn,
+ [Values(2u, 0u)] uint rm,
+ [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
+ [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong a,
+ [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong b,
+ [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+ {
+ opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
+ opcodes |= ((size & 3) << 22);
+
+ Vector128<float> v0 = MakeVectorE0E1(z, z);
+ Vector128<float> v1 = MakeVectorE0E1(a, a);
+ Vector128<float> v2 = MakeVectorE0E1(b, b);
+
+ SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
+
+ CompareAgainstUnicorn();
+ }
+
[Test, Pairwise, Description("ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Orn_V_8B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs b/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
index f026158c..9a295d5e 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
@@ -258,14 +258,15 @@ namespace Ryujinx.Tests.Cpu
}
#endregion
- private const int RndCnt = 2;
+ private const int RndCnt = 2;
+ private const int RndCntShift = 2;
[Test, Pairwise, Description("SHL <V><d>, <V><n>, #<shift>")]
public void Shl_S_D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
- [Range(0u, 63u)] uint shift)
+ [Values(0u, 63u)] [Random(1u, 62u, RndCntShift)] uint shift)
{
uint immHb = (64 + shift) & 0x7F;
@@ -286,7 +287,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
- [Range(0u, 7u)] uint shift,
+ [Values(0u, 7u)] [Random(1u, 6u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
{
uint immHb = (8 + shift) & 0x7F;
@@ -309,7 +310,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
- [Range(0u, 15u)] uint shift,
+ [Values(0u, 15u)] [Random(1u, 14u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
{
uint immHb = (16 + shift) & 0x7F;
@@ -332,7 +333,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
- [Range(0u, 31u)] uint shift,
+ [Values(0u, 31u)] [Random(1u, 30u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
{
uint immHb = (32 + shift) & 0x7F;
@@ -355,7 +356,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
- [Range(0u, 63u)] uint shift)
+ [Values(0u, 63u)] [Random(1u, 62u, RndCntShift)] uint shift)
{
uint immHb = (64 + shift) & 0x7F;
@@ -377,7 +378,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
- [Range(0u, 7u)] uint shift,
+ [Values(0u, 7u)] [Random(1u, 6u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <8B8H, 16B8H>
{
uint immHb = (8 + shift) & 0x7F;
@@ -400,7 +401,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
- [Range(0u, 15u)] uint shift,
+ [Values(0u, 15u)] [Random(1u, 14u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <4H4S, 8H4S>
{
uint immHb = (16 + shift) & 0x7F;
@@ -423,7 +424,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
- [Range(0u, 31u)] uint shift,
+ [Values(0u, 31u)] [Random(1u, 30u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <2S2D, 4S2D>
{
uint immHb = (32 + shift) & 0x7F;
@@ -446,7 +447,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
- [Range(1u, 64u)] uint shift)
+ [Values(1u, 64u)] [Random(2u, 63u, RndCntShift)] uint shift)
{
uint immHb = (128 - shift) & 0x7F;
@@ -467,7 +468,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
- [Range(1u, 8u)] uint shift,
+ [Values(1u, 8u)] [Random(2u, 7u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
{
uint immHb = (16 - shift) & 0x7F;
@@ -490,7 +491,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
- [Range(1u, 16u)] uint shift,
+ [Values(1u, 16u)] [Random(2u, 15u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
{
uint immHb = (32 - shift) & 0x7F;
@@ -513,7 +514,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
- [Range(1u, 32u)] uint shift,
+ [Values(1u, 32u)] [Random(2u, 31u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
{
uint immHb = (64 - shift) & 0x7F;
@@ -536,7 +537,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
- [Range(1u, 64u)] uint shift)
+ [Values(1u, 64u)] [Random(2u, 63u, RndCntShift)] uint shift)
{
uint immHb = (128 - shift) & 0x7F;
@@ -557,7 +558,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
- [Range(1u, 8u)] uint shift,
+ [Values(1u, 8u)] [Random(2u, 7u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <8H8B, 8H16B>
{
uint immHb = (16 - shift) & 0x7F;
@@ -580,7 +581,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
- [Range(1u, 16u)] uint shift,
+ [Values(1u, 16u)] [Random(2u, 15u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <4S4H, 4S8H>
{
uint immHb = (32 - shift) & 0x7F;
@@ -603,7 +604,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
- [Range(1u, 32u)] uint shift,
+ [Values(1u, 32u)] [Random(2u, 31u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <2D2S, 2D4S>
{
uint immHb = (64 - shift) & 0x7F;
@@ -626,7 +627,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_1H_")] [Random(RndCnt)] ulong z,
[ValueSource("_1H_")] [Random(RndCnt)] ulong a,
- [Range(1u, 8u)] uint shift)
+ [Values(1u, 8u)] [Random(2u, 7u, RndCntShift)] uint shift)
{
uint immHb = (16 - shift) & 0x7F;
@@ -647,7 +648,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_1S_")] [Random(RndCnt)] ulong z,
[ValueSource("_1S_")] [Random(RndCnt)] ulong a,
- [Range(1u, 16u)] uint shift)
+ [Values(1u, 16u)] [Random(2u, 15u, RndCntShift)] uint shift)
{
uint immHb = (32 - shift) & 0x7F;
@@ -668,7 +669,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
- [Range(1u, 32u)] uint shift)
+ [Values(1u, 32u)] [Random(2u, 31u, RndCntShift)] uint shift)
{
uint immHb = (64 - shift) & 0x7F;
@@ -689,7 +690,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
- [Range(1u, 8u)] uint shift,
+ [Values(1u, 8u)] [Random(2u, 7u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <8H8B, 8H16B>
{
uint immHb = (16 - shift) & 0x7F;
@@ -712,7 +713,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
- [Range(1u, 16u)] uint shift,
+ [Values(1u, 16u)] [Random(2u, 15u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <4S4H, 4S8H>
{
uint immHb = (32 - shift) & 0x7F;
@@ -735,7 +736,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0u)] uint rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
- [Range(1u, 32u)] uint shift,
+ [Values(1u, 32u)] [Random(2u, 31u, RndCntShift)] uint shift,
[Values(0b0u, 0b1u)] uint q) // <2D2S, 2D4S>
{
uint immHb = (64 - shift) & 0x7F;
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-09 11:54:39 +0000