diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-07-17 06:21:40 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-17 14:21:40 +1000 |
| commit | 88619d71b8e4840218c68b712aa184098d2dbccf (patch) | |
| tree | 1994bfc8353c973c663f60d6f6f803cd7285723d /Ryujinx.Tests/Cpu | |
| parent | 9f6b24edfddf871320290463437b3f3cb7e29006 (diff) | |
CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390)
Diffstat (limited to 'Ryujinx.Tests/Cpu')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | 97 |
1 files changed, 43 insertions, 54 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs index 1581e850..dbe69124 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs @@ -13,6 +13,15 @@ namespace Ryujinx.Tests.Cpu #if SimdReg32 #region "ValueSource (Opcodes)" + private static uint[] _V_Add_Sub_Wide_I_() + { + return new uint[] + { + 0xf2800100u, // VADDW.S8 Q0, Q0, D0 + 0xf2800300u // VSUBW.S8 Q0, Q0, D0 + }; + } + private static uint[] _Vp_Add_Max_Min_F_() { return new uint[] @@ -38,60 +47,6 @@ namespace Ryujinx.Tests.Cpu #endregion #region "ValueSource (Types)" - private static ulong[] _1B1H1S1D_() - { - return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful, - 0x0000000000000080ul, 0x00000000000000FFul, - 0x0000000000007FFFul, 0x0000000000008000ul, - 0x000000000000FFFFul, 0x000000007FFFFFFFul, - 0x0000000080000000ul, 0x00000000FFFFFFFFul, - 0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul, - 0xFFFFFFFFFFFFFFFFul }; - } - - private static ulong[] _1D_() - { - return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; - } - - private static ulong[] _1H1S_() - { - return new ulong[] { 0x0000000000000000ul, 0x0000000000007FFFul, - 0x0000000000008000ul, 0x000000000000FFFFul, - 0x000000007FFFFFFFul, 0x0000000080000000ul, - 0x00000000FFFFFFFFul }; - } - - private static ulong[] _4H2S_() - { - return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, - 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, - 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; - } - - private static ulong[] _4H2S1D_() - { - return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, - 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, - 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; - } - - private static ulong[] _8B_() - { - return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, - 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul }; - } - - private static ulong[] _8B4H2S_() - { - return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, - 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, - 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, - 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; - } - private static ulong[] _8B4H2S1D_() { return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, @@ -267,6 +222,40 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } + [Test, Pairwise] + public void V_Add_Sub_Wide_I([ValueSource("_V_Add_Sub_Wide_I_")] uint opcode, + [Range(0u, 5u)] uint rd, + [Range(0u, 5u)] uint rn, + [Range(0u, 5u)] uint rm, + [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong z, + [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong a, + [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong b, + [Values(0u, 1u, 2u)] uint size, // <SU8, SU16, SU32> + [Values] bool u) // <S, U> + { + if (u) + { + opcode |= 1 << 24; + } + + rd >>= 1; rd <<= 1; + rn >>= 1; rn <<= 1; + + opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); + opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + + opcode |= (size & 0x3) << 20; + + V128 v0 = MakeVectorE0E1(z, ~z); + V128 v1 = MakeVectorE0E1(a, ~a); + V128 v2 = MakeVectorE0E1(b, ~b); + + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2); + + CompareAgainstUnicorn(); + } + [Test, Pairwise, Description("VCMP.f<size> Vd, Vm")] public void Vcmp([Values(2u, 3u)] uint size, [ValueSource("_1S_F_")] ulong a, |
