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2018-09-08Remove old Tester, update Tests (some reworks). (#400)LDj3SNuD
2018-09-01Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_...LDj3SNuD
2018-09-01Ryujinx.Tests: Add unicorn to test framework (#389)Merry
2018-08-27Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)LDj3SNuD
2018-08-20Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). ...LDj3SNuD
2018-08-16Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed...LDj3SNuD
2018-08-15More flexible memory manager (#307)gdkchan
2018-08-13Add Sadalp_V, Saddlp_V, Uadalp_V, Uaddlp_V instructions; add 8 Tests. (#340)LDj3SNuD
2018-08-10Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. N...LDj3SNuD
2018-08-05More accurate impl of FMINNM/FMAXNM, add vector variants (#296)gdkchan
2018-08-04Add SQADD, UQADD, SQSUB, UQSUB, SUQADD, USQADD, SQABS, SQNEG (Scalar, Vector)...LDj3SNuD
2018-07-18Implement Ssubw_V and Usubw_V instructions. (#287)LDj3SNuD
2018-07-15Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& P...LDj3SNuD
2018-07-12AInstEmitSimdCvt: Half-precision to single-precision conversion (#235)Merry
2018-07-08ChocolArm64: More accurate implementation of Frecpe & Frecps (#228)Merry
2018-07-03Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Impr...LDj3SNuD
2018-06-30Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V...LDj3SNuD
2018-06-25Add Sqxtun_S, Sqxtun_V with 3 tests. (#188)LDj3SNuD
2018-06-25Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32c...LDj3SNuD
2018-06-18Add Cmeq_S, Cmge_S, Cmgt_S, Cmhi_S, Cmhs_S, Cmle_S, Cmlt_S (Reg, Zero) & Cmts...LDj3SNuD
2018-06-10Rename Ryujinx.Core to Ryujinx.HLE and add a separate project for a future LL...gdkchan
2018-05-11Add intrinsics support (#121)gdkchan
2018-04-29Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). (#110)LDj3SNuD
2018-04-25Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_...LDj3SNuD
2018-04-21Fix Addp_S in AOpCodeTable. Add 5 Tests: ADDP (scalar), ADDP (vector), ADDV. ...LDj3SNuD
2018-04-20Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tes...LDj3SNuD
2018-04-19Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89)MS-DOS1999
2018-04-18Add 151 complete tests for 71 base instructions of types: Alu; AluImm; AluRs;...LDj3SNuD
2018-04-12Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77)LDj3SNuD
2018-04-08Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vecto...LDj3SNuD
2018-04-05Implement Frsqrte_S (#72)Merry
2018-03-23Add Frint Instructions and Tests (#62)MS-DOS1999
2018-03-12Allow more than one process, free resources on process dispose, implement Svc...gdkchan
2018-03-10Allow to enable/disable memory checks even on release mode through the flag, ...gdkchan
2018-03-09Disable memory checks by default, even on debug, move ram memory allocation i...gdkchan
2018-03-05Add Frintx_S, ASRV test, update ADCS, use Assert.Multiple and indent (#44)MS-DOS1999
2018-02-27Change SvcGetInfo 5 to return actual heap size, remove AMemoryAlloc since it ...gdkchan
2018-02-25Added initial support for function names from symbol table on the cpu with tr...gdkchan
2018-02-24Update ADC test, add WZR/WSP, ADCS, SBCS test (#37)MS-DOS1999
2018-02-23Add flags parameters in singleOpcode function, and add ADC Test (#36)MS-DOS1999
2018-02-23Review of cpu tests and creation of a class for mixed cpu tests. (#35)LDj3SNuD
2018-02-20Implement Zip1, Zip2 (#25)Merry
2018-02-19Tests: Add Fmax_S test (#23)Merry
2018-02-18Rename ARegisters to AThreadStategdkchan
2018-02-15Add some tests (#18)Merry
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