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authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2018-08-10 19:27:15 +0200
committergdkchan <gab.dark.100@gmail.com>2018-08-10 14:27:15 -0300
commit02a6fdcd1369cea926a1ad549ef69dbff60f034a (patch)
tree39f569023d300b2dd2b5a1132221658d7590648d /Ryujinx.Tests/Cpu
parent267af1f0f775d11b36dab0d1276188f907604584 (diff)
Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. Now all saturating methods are on ASoftFallback. (#334)
* Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update ASoftFallback.cs * Update CpuTestAlu.cs * Update CpuTestAluImm.cs * Update CpuTestAluRs.cs * Update CpuTestAluRx.cs * Update CpuTestBfm.cs * Update CpuTestCcmpImm.cs * Update CpuTestCcmpReg.cs * Update CpuTestCsel.cs * Update CpuTestMov.cs * Update CpuTestMul.cs * Update Ryujinx.Tests.csproj * Update Ryujinx.csproj * Update Luea.csproj * Update Ryujinx.ShaderTools.csproj * Address PR feedback (further tested). * Address PR feedback.
Diffstat (limited to 'Ryujinx.Tests/Cpu')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestAlu.cs2
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestAluImm.cs2
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestAluRs.cs2
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestAluRx.cs2
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestBfm.cs2
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs2
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs2
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestCsel.cs2
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestMov.cs2
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestMul.cs2
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimd.cs126
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdReg.cs421
-rw-r--r--Ryujinx.Tests/Cpu/Tester/Instructions.cs204
13 files changed, 600 insertions, 171 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs
index 564fadec..c89cb646 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
- [Category("Alu"), Ignore("Tested: first half of 2018.")]
+ [Category("Alu"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestAlu : CpuTest
{
#if Alu
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
index 5d1f0b6b..d436d65f 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
- [Category("AluImm"), Ignore("Tested: first half of 2018.")]
+ [Category("AluImm"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestAluImm : CpuTest
{
#if AluImm
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
index b81f7100..880794cf 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
- [Category("AluRs"), Ignore("Tested: first half of 2018.")]
+ [Category("AluRs"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestAluRs : CpuTest
{
#if AluRs
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRx.cs b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs
index 26169bca..d6cf8dc4 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluRx.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
- [Category("AluRx"), Ignore("Tested: first half of 2018.")]
+ [Category("AluRx"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestAluRx : CpuTest
{
#if AluRx
diff --git a/Ryujinx.Tests/Cpu/CpuTestBfm.cs b/Ryujinx.Tests/Cpu/CpuTestBfm.cs
index 2952bca4..0a2f9ad3 100644
--- a/Ryujinx.Tests/Cpu/CpuTestBfm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestBfm.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
- [Category("Bfm"), Ignore("Tested: first half of 2018.")]
+ [Category("Bfm"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestBfm : CpuTest
{
#if Bfm
diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs
index 38d73878..7ba44ed9 100644
--- a/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
- [Category("CcmpImm"), Ignore("Tested: first half of 2018.")]
+ [Category("CcmpImm"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestCcmpImm : CpuTest
{
#if CcmpImm
diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs
index eb1c3abf..82556464 100644
--- a/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
- [Category("CcmpReg"), Ignore("Tested: first half of 2018.")]
+ [Category("CcmpReg"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestCcmpReg : CpuTest
{
#if CcmpReg
diff --git a/Ryujinx.Tests/Cpu/CpuTestCsel.cs b/Ryujinx.Tests/Cpu/CpuTestCsel.cs
index 9dd61957..fef56fee 100644
--- a/Ryujinx.Tests/Cpu/CpuTestCsel.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestCsel.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
- [Category("Csel"), Ignore("Tested: first half of 2018.")]
+ [Category("Csel"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestCsel : CpuTest
{
#if Csel
diff --git a/Ryujinx.Tests/Cpu/CpuTestMov.cs b/Ryujinx.Tests/Cpu/CpuTestMov.cs
index 9c7e3255..db544f86 100644
--- a/Ryujinx.Tests/Cpu/CpuTestMov.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestMov.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
- [Category("Mov"), Ignore("Tested: first half of 2018.")]
+ [Category("Mov"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestMov : CpuTest
{
#if Mov
diff --git a/Ryujinx.Tests/Cpu/CpuTestMul.cs b/Ryujinx.Tests/Cpu/CpuTestMul.cs
index 9bdc1fa6..19b8ecd0 100644
--- a/Ryujinx.Tests/Cpu/CpuTestMul.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestMul.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
- [Category("Mul"), Ignore("Tested: first half of 2018.")]
+ [Category("Mul"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestMul : CpuTest
{
#if Mul
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
index 88c5981c..bb60273a 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
@@ -90,7 +90,7 @@ namespace Ryujinx.Tests.Cpu
private const int RndCnt = 1;
[Test, Description("ABS <V><d>, <V><n>")]
- public void Abs_S_D([Values(0u)] uint Rd,
+ public void Abs_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@@ -115,7 +115,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
- public void Abs_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Abs_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -142,7 +142,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
- public void Abs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Abs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -169,7 +169,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("ADDP <V><d>, <Vn>.<T>")]
- public void Addp_S_2DD([Values(0u)] uint Rd,
+ public void Addp_S_2DD([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@@ -194,7 +194,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("ADDV <V><d>, <Vn>.<T>")]
- public void Addv_V_8BB_4HH([Values(0u)] uint Rd,
+ public void Addv_V_8BB_4HH([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
@@ -221,7 +221,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("ADDV <V><d>, <Vn>.<T>")]
- public void Addv_V_16BB_8HH_4SS([Values(0u)] uint Rd,
+ public void Addv_V_16BB_8HH_4SS([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -248,7 +248,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
- public void Cls_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cls_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -275,7 +275,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
- public void Cls_V_16B_8H_4S([Values(0u)] uint Rd,
+ public void Cls_V_16B_8H_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -302,7 +302,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
- public void Clz_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Clz_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -329,7 +329,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
- public void Clz_V_16B_8H_4S([Values(0u)] uint Rd,
+ public void Clz_V_16B_8H_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -356,7 +356,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMEQ <V><d>, <V><n>, #0")]
- public void Cmeq_S_D([Values(0u)] uint Rd,
+ public void Cmeq_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@@ -381,7 +381,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMEQ <Vd>.<T>, <Vn>.<T>, #0")]
- public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -408,7 +408,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMEQ <Vd>.<T>, <Vn>.<T>, #0")]
- public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -435,7 +435,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGE <V><d>, <V><n>, #0")]
- public void Cmge_S_D([Values(0u)] uint Rd,
+ public void Cmge_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@@ -460,7 +460,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGE <Vd>.<T>, <Vn>.<T>, #0")]
- public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -487,7 +487,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGE <Vd>.<T>, <Vn>.<T>, #0")]
- public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -514,7 +514,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGT <V><d>, <V><n>, #0")]
- public void Cmgt_S_D([Values(0u)] uint Rd,
+ public void Cmgt_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@@ -539,7 +539,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGT <Vd>.<T>, <Vn>.<T>, #0")]
- public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -566,7 +566,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGT <Vd>.<T>, <Vn>.<T>, #0")]
- public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -593,7 +593,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLE <V><d>, <V><n>, #0")]
- public void Cmle_S_D([Values(0u)] uint Rd,
+ public void Cmle_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@@ -618,7 +618,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLE <Vd>.<T>, <Vn>.<T>, #0")]
- public void Cmle_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cmle_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -645,7 +645,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLE <Vd>.<T>, <Vn>.<T>, #0")]
- public void Cmle_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Cmle_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -672,7 +672,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLT <V><d>, <V><n>, #0")]
- public void Cmlt_S_D([Values(0u)] uint Rd,
+ public void Cmlt_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@@ -697,7 +697,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLT <Vd>.<T>, <Vn>.<T>, #0")]
- public void Cmlt_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cmlt_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -724,7 +724,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLT <Vd>.<T>, <Vn>.<T>, #0")]
- public void Cmlt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Cmlt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -751,7 +751,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CNT <Vd>.<T>, <Vn>.<T>")]
- public void Cnt_V_8B([Values(0u)] uint Rd,
+ public void Cnt_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@@ -776,7 +776,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CNT <Vd>.<T>, <Vn>.<T>")]
- public void Cnt_V_16B([Values(0u)] uint Rd,
+ public void Cnt_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@@ -801,7 +801,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("NEG <V><d>, <V><n>")]
- public void Neg_S_D([Values(0u)] uint Rd,
+ public void Neg_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@@ -826,7 +826,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
- public void Neg_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Neg_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -853,7 +853,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
- public void Neg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Neg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -880,7 +880,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("NOT <Vd>.<T>, <Vn>.<T>")]
- public void Not_V_8B([Values(0u)] uint Rd,
+ public void Not_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@@ -905,7 +905,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("NOT <Vd>.<T>, <Vn>.<T>")]
- public void Not_V_16B([Values(0u)] uint Rd,
+ public void Not_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@@ -930,7 +930,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
- public void Rbit_V_8B([Values(0u)] uint Rd,
+ public void Rbit_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@@ -955,7 +955,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
- public void Rbit_V_16B([Values(0u)] uint Rd,
+ public void Rbit_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@@ -980,7 +980,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
- public void Rev16_V_8B([Values(0u)] uint Rd,
+ public void Rev16_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@@ -1005,7 +1005,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
- public void Rev16_V_16B([Values(0u)] uint Rd,
+ public void Rev16_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@@ -1030,7 +1030,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
- public void Rev32_V_8B_4H([Values(0u)] uint Rd,
+ public void Rev32_V_8B_4H([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
@@ -1057,7 +1057,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
- public void Rev32_V_16B_8H([Values(0u)] uint Rd,
+ public void Rev32_V_16B_8H([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
@@ -1084,7 +1084,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
- public void Rev64_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Rev64_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -1111,7 +1111,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
- public void Rev64_V_16B_8H_4S([Values(0u)] uint Rd,
+ public void Rev64_V_16B_8H_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -1138,7 +1138,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQABS <V><d>, <V><n>")]
- public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd,
+ public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
@@ -1169,7 +1169,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
- public void Sqabs_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Sqabs_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -1200,7 +1200,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
- public void Sqabs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Sqabs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -1231,7 +1231,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQNEG <V><d>, <V><n>")]
- public void Sqneg_S_B_H_S_D([Values(0u)] uint Rd,
+ public void Sqneg_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
@@ -1262,7 +1262,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
- public void Sqneg_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Sqneg_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -1293,7 +1293,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
- public void Sqneg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Sqneg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -1324,7 +1324,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTN <Vb><d>, <Va><n>")]
- public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
+ public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
@@ -1355,7 +1355,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
- public void Sqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
+ public void Sqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -1386,7 +1386,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
- public void Sqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
+ public void Sqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -1417,7 +1417,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTUN <Vb><d>, <Va><n>")]
- public void Sqxtun_S_HB_SH_DS([Values(0u)] uint Rd,
+ public void Sqxtun_S_HB_SH_DS([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
@@ -1448,7 +1448,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
- public void Sqxtun_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
+ public void Sqxtun_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -1479,7 +1479,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
- public void Sqxtun_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
+ public void Sqxtun_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -1510,7 +1510,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SUQADD <V><d>, <V><n>")]
- public void Suqadd_S_B_H_S_D([Values(0u)] uint Rd,
+ public void Suqadd_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
@@ -1541,7 +1541,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
- public void Suqadd_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Suqadd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -1572,7 +1572,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
- public void Suqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Suqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -1603,7 +1603,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("UQXTN <Vb><d>, <Va><n>")]
- public void Uqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
+ public void Uqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
@@ -1634,7 +1634,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
- public void Uqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
+ public void Uqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -1665,7 +1665,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
- public void Uqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
+ public void Uqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -1696,7 +1696,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("USQADD <V><d>, <V><n>")]
- public void Usqadd_S_B_H_S_D([Values(0u)] uint Rd,
+ public void Usqadd_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
@@ -1727,7 +1727,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
- public void Usqadd_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Usqadd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@@ -1758,7 +1758,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
- public void Usqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Usqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -1789,7 +1789,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
- public void Xtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
+ public void Xtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@@ -1816,7 +1816,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
- public void Xtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
+ public void Xtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
index e6cfcbde..c1cf812e 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
@@ -39,6 +39,21 @@ namespace Ryujinx.Tests.Cpu
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
+ private static ulong[] _1H1S_()
+ {
+ return new ulong[] { 0x0000000000000000ul, 0x0000000000007FFFul,
+ 0x0000000000008000ul, 0x000000000000FFFFul,
+ 0x000000007FFFFFFFul, 0x0000000080000000ul,
+ 0x00000000FFFFFFFFul };
+ }
+
+ private static ulong[] _4H2S_()
+ {
+ return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+ }
+
private static ulong[] _4H2S1D_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
@@ -74,7 +89,7 @@ namespace Ryujinx.Tests.Cpu
private const int RndCnt = 4;
[Test, Pairwise, Description("ADD <V><d>, <V><n>, <V><m>")]
- public void Add_S_D([Values(0u)] uint Rd,
+ public void Add_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
@@ -103,7 +118,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Add_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Add_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -134,7 +149,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Add_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Add_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -165,7 +180,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
- public void Addhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
+ public void Addhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -196,7 +211,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
- public void Addhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
+ public void Addhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -227,7 +242,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Addp_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Addp_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -258,7 +273,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Addp_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Addp_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -289,7 +304,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void And_V_8B([Values(0u)] uint Rd,
+ public void And_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -318,7 +333,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void And_V_16B([Values(0u)] uint Rd,
+ public void And_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -347,7 +362,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Bic_V_8B([Values(0u)] uint Rd,
+ public void Bic_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -376,7 +391,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Bic_V_16B([Values(0u)] uint Rd,
+ public void Bic_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -405,7 +420,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Bif_V_8B([Values(0u)] uint Rd,
+ public void Bif_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -434,7 +449,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Bif_V_16B([Values(0u)] uint Rd,
+ public void Bif_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -463,7 +478,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Bit_V_8B([Values(0u)] uint Rd,
+ public void Bit_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -492,7 +507,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Bit_V_16B([Values(0u)] uint Rd,
+ public void Bit_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -521,7 +536,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Bsl_V_8B([Values(0u)] uint Rd,
+ public void Bsl_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -550,7 +565,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Bsl_V_16B([Values(0u)] uint Rd,
+ public void Bsl_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -579,7 +594,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMEQ <V><d>, <V><n>, <V><m>")]
- public void Cmeq_S_D([Values(0u)] uint Rd,
+ public void Cmeq_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
@@ -608,7 +623,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -639,7 +654,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -670,7 +685,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGE <V><d>, <V><n>, <V><m>")]
- public void Cmge_S_D([Values(0u)] uint Rd,
+ public void Cmge_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
@@ -699,7 +714,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -730,7 +745,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -761,7 +776,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGT <V><d>, <V><n>, <V><m>")]
- public void Cmgt_S_D([Values(0u)] uint Rd,
+ public void Cmgt_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
@@ -790,7 +805,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -821,7 +836,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -852,7 +867,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMHI <V><d>, <V><n>, <V><m>")]
- public void Cmhi_S_D([Values(0u)] uint Rd,
+ public void Cmhi_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
@@ -881,7 +896,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMHI <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmhi_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cmhi_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -912,7 +927,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMHI <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmhi_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Cmhi_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -943,7 +958,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMHS <V><d>, <V><n>, <V><m>")]
- public void Cmhs_S_D([Values(0u)] uint Rd,
+ public void Cmhs_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
@@ -972,7 +987,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMHS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmhs_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cmhs_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1003,7 +1018,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMHS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmhs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Cmhs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -1034,7 +1049,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMTST <V><d>, <V><n>, <V><m>")]
- public void Cmtst_S_D([Values(0u)] uint Rd,
+ public void Cmtst_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
@@ -1063,7 +1078,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmtst_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Cmtst_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1094,7 +1109,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Cmtst_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Cmtst_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -1125,7 +1140,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Eor_V_8B([Values(0u)] uint Rd,
+ public void Eor_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -1154,7 +1169,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Eor_V_16B([Values(0u)] uint Rd,
+ public void Eor_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -1183,7 +1198,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Orn_V_8B([Values(0u)] uint Rd,
+ public void Orn_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -1212,7 +1227,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Orn_V_16B([Values(0u)] uint Rd,
+ public void Orn_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -1241,7 +1256,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Orr_V_8B([Values(0u)] uint Rd,
+ public void Orr_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -1270,7 +1285,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Orr_V_16B([Values(0u)] uint Rd,
+ public void Orr_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
@@ -1299,7 +1314,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("RADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
- public void Raddhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
+ public void Raddhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -1330,7 +1345,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("RADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
- public void Raddhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
+ public void Raddhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -1361,7 +1376,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("RSUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
- public void Rsubhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
+ public void Rsubhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -1392,7 +1407,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("RSUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
- public void Rsubhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
+ public void Rsubhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -1423,7 +1438,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Saba_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Saba_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1454,7 +1469,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Saba_V_16B_8H_4S([Values(0u)] uint Rd,
+ public void Saba_V_16B_8H_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1485,7 +1500,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
- public void Sabal_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd,
+ public void Sabal_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1516,7 +1531,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
- public void Sabal_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
+ public void Sabal_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1547,7 +1562,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Sabd_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Sabd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1578,7 +1593,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Sabd_V_16B_8H_4S([Values(0u)] uint Rd,
+ public void Sabd_V_16B_8H_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1609,7 +1624,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
- public void Sabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd,
+ public void Sabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1640,7 +1655,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
- public void Sabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
+ public void Sabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1671,7 +1686,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
- public void Saddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
+ public void Saddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -1702,7 +1717,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
- public void Saddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
+ public void Saddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -1733,7 +1748,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SQADD <V><d>, <V><n>, <V><m>")]
- public void Sqadd_S_B_H_S_D([Values(0u)] uint Rd,
+ public void Sqadd_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
@@ -1768,7 +1783,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Sqadd_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Sqadd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1803,7 +1818,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Sqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Sqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -1837,8 +1852,218 @@ namespace Ryujinx.Tests.Cpu
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
+ [Test, Pairwise, Description("SQDMULH <V><d>, <V><n>, <V><m>")]
+ public void Sqdmulh_S_H_S([Values(0u)] uint Rd,
+ [Values(1u, 0u)] uint Rn,
+ [Values(2u, 0u)] uint Rm,
+ [ValueSource("_1H1S_")] [Random(RndCnt)] ulong Z,
+ [ValueSource("_1H1S_")] [Random(RndCnt)] ulong A,
+ [ValueSource("_1H1S_")] [Random(RndCnt)] ulong B,
+ [Values(0b01u, 0b10u)] uint size) // <H, S>
+ {
+ uint Opcode = 0x5E20B400; // SQDMULH B0, B0, B0 (RESERVED)
+ Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+ Opcode |= ((size & 3) << 22);
+ Bits Op = new Bits(Opcode);
+
+ int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
+
+ Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+ Vector128<float> V1 = MakeVectorE0(A);
+ Vector128<float> V2 = MakeVectorE0(B);
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
+
+ AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+ AArch64.V(1, new Bits(A));
+ AArch64.V(2, new Bits(B));
+ Shared.FPSR = new Bits((uint)Fpsr);
+ SimdFp.Sqdmulh_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
+ }
+
+ [Test, Pairwise, Description("SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Sqdmulh_V_4H_2S([Values(0u)] uint Rd,
+ [Values(1u, 0u)] uint Rn,
+ [Values(2u, 0u)] uint Rm,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong A,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B,
+ [Values(0b01u, 0b10u)] uint size) // <4H, 2S>
+ {
+ uint Opcode = 0x0E20B400; // SQDMULH V0.8B, V0.8B, V0.8B (RESERVED)
+ Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+ Opcode |= ((size & 3) << 22);
+ Bits Op = new Bits(Opcode);
+
+ int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
+
+ Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+ Vector128<float> V1 = MakeVectorE0(A);
+ Vector128<float> V2 = MakeVectorE0(B);
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
+
+ AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+ AArch64.V(1, new Bits(A));
+ AArch64.V(2, new Bits(B));
+ Shared.FPSR = new Bits((uint)Fpsr);
+ SimdFp.Sqdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
+ }
+
+ [Test, Pairwise, Description("SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Sqdmulh_V_8H_4S([Values(0u)] uint Rd,
+ [Values(1u, 0u)] uint Rn,
+ [Values(2u, 0u)] uint Rm,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong A,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B,
+ [Values(0b01u, 0b10u)] uint size) // <8H, 4S>
+ {
+ uint Opcode = 0x4E20B400; // SQDMULH V0.16B, V0.16B, V0.16B (RESERVED)
+ Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+ Opcode |= ((size & 3) << 22);
+ Bits Op = new Bits(Opcode);
+
+ int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
+
+ Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+ Vector128<float> V1 = MakeVectorE0E1(A, A);
+ Vector128<float> V2 = MakeVectorE0E1(B, B);
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
+
+ AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+ AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+ AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+ Shared.FPSR = new Bits((uint)Fpsr);
+ SimdFp.Sqdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
+ }
+
+ [Test, Pairwise, Description("SQRDMULH <V><d>, <V><n>, <V><m>")]
+ public void Sqrdmulh_S_H_S([Values(0u)] uint Rd,
+ [Values(1u, 0u)] uint Rn,
+ [Values(2u, 0u)] uint Rm,
+ [ValueSource("_1H1S_")] [Random(RndCnt)] ulong Z,
+ [ValueSource("_1H1S_")] [Random(RndCnt)] ulong A,
+ [ValueSource("_1H1S_")] [Random(RndCnt)] ulong B,
+ [Values(0b01u, 0b10u)] uint size) // <H, S>
+ {
+ uint Opcode = 0x7E20B400; // SQRDMULH B0, B0, B0 (RESERVED)
+ Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+ Opcode |= ((size & 3) << 22);
+ Bits Op = new Bits(Opcode);
+
+ int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
+
+ Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+ Vector128<float> V1 = MakeVectorE0(A);
+ Vector128<float> V2 = MakeVectorE0(B);
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
+
+ AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+ AArch64.V(1, new Bits(A));
+ AArch64.V(2, new Bits(B));
+ Shared.FPSR = new Bits((uint)Fpsr);
+ SimdFp.Sqrdmulh_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
+ }
+
+ [Test, Pairwise, Description("SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Sqrdmulh_V_4H_2S([Values(0u)] uint Rd,
+ [Values(1u, 0u)] uint Rn,
+ [Values(2u, 0u)] uint Rm,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong A,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B,
+ [Values(0b01u, 0b10u)] uint size) // <4H, 2S>
+ {
+ uint Opcode = 0x2E20B400; // SQRDMULH V0.8B, V0.8B, V0.8B (RESERVED)
+ Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+ Opcode |= ((size & 3) << 22);
+ Bits Op = new Bits(Opcode);
+
+ int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
+
+ Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+ Vector128<float> V1 = MakeVectorE0(A);
+ Vector128<float> V2 = MakeVectorE0(B);
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
+
+ AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+ AArch64.V(1, new Bits(A));
+ AArch64.V(2, new Bits(B));
+ Shared.FPSR = new Bits((uint)Fpsr);
+ SimdFp.Sqrdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
+ }
+
+ [Test, Pairwise, Description("SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Sqrdmulh_V_8H_4S([Values(0u)] uint Rd,
+ [Values(1u, 0u)] uint Rn,
+ [Values(2u, 0u)] uint Rm,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong A,
+ [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B,
+ [Values(0b01u, 0b10u)] uint size) // <8H, 4S>
+ {
+ uint Opcode = 0x6E20B400; // SQRDMULH V0.16B, V0.16B, V0.16B (RESERVED)
+ Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+ Opcode |= ((size & 3) << 22);
+ Bits Op = new Bits(Opcode);
+
+ int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
+
+ Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+ Vector128<float> V1 = MakeVectorE0E1(A, A);
+ Vector128<float> V2 = MakeVectorE0E1(B, B);
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
+
+ AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+ AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+ AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+ Shared.FPSR = new Bits((uint)Fpsr);
+ SimdFp.Sqrdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
+ }
+
[Test, Pairwise, Description("SQSUB <V><d>, <V><n>, <V><m>")]
- public void Sqsub_S_B_H_S_D([Values(0u)] uint Rd,
+ public void Sqsub_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
@@ -1873,7 +2098,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Sqsub_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Sqsub_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -1908,7 +2133,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Sqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Sqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -1943,7 +2168,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SSUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
- public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
+ public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -1974,7 +2199,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SSUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
- public void Ssubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
+ public void Ssubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2005,7 +2230,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SUB <V><d>, <V><n>, <V><m>")]
- public void Sub_S_D([Values(0u)] uint Rd,
+ public void Sub_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
@@ -2034,7 +2259,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Sub_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Sub_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2065,7 +2290,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Sub_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Sub_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2096,7 +2321,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
- public void Subhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
+ public void Subhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2127,7 +2352,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
- public void Subhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
+ public void Subhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2158,7 +2383,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Trn1_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Trn1_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2189,7 +2414,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Trn1_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Trn1_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2220,7 +2445,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Trn2_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Trn2_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2251,7 +2476,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Trn2_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Trn2_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2282,7 +2507,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uaba_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Uaba_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2313,7 +2538,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uaba_V_16B_8H_4S([Values(0u)] uint Rd,
+ public void Uaba_V_16B_8H_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2344,7 +2569,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
- public void Uabal_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd,
+ public void Uabal_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2375,7 +2600,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UABAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
- public void Uabal_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
+ public void Uabal_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2406,7 +2631,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uabd_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Uabd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2437,7 +2662,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uabd_V_16B_8H_4S([Values(0u)] uint Rd,
+ public void Uabd_V_16B_8H_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2468,7 +2693,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
- public void Uabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd,
+ public void Uabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2499,7 +2724,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UABDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")]
- public void Uabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
+ public void Uabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2530,7 +2755,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
- public void Uaddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
+ public void Uaddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2561,7 +2786,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
- public void Uaddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
+ public void Uaddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2592,7 +2817,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UQADD <V><d>, <V><n>, <V><m>")]
- public void Uqadd_S_B_H_S_D([Values(0u)] uint Rd,
+ public void Uqadd_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
@@ -2627,7 +2852,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uqadd_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Uqadd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2662,7 +2887,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Uqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2697,7 +2922,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UQSUB <V><d>, <V><n>, <V><m>")]
- public void Uqsub_S_B_H_S_D([Values(0u)] uint Rd,
+ public void Uqsub_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
@@ -2732,7 +2957,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uqsub_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Uqsub_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2767,7 +2992,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Uqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2802,7 +3027,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
- public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
+ public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2833,7 +3058,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
- public void Usubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
+ public void Usubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2864,7 +3089,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uzp1_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Uzp1_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2895,7 +3120,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uzp1_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Uzp1_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2926,7 +3151,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uzp2_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Uzp2_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -2957,7 +3182,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Uzp2_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Uzp2_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -2988,7 +3213,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Zip1_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Zip1_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -3019,7 +3244,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Zip1_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Zip1_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
@@ -3050,7 +3275,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Zip2_V_8B_4H_2S([Values(0u)] uint Rd,
+ public void Zip2_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
@@ -3081,7 +3306,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
- public void Zip2_V_16B_8H_4S_2D([Values(0u)] uint Rd,
+ public void Zip2_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
diff --git a/Ryujinx.Tests/Cpu/Tester/Instructions.cs b/Ryujinx.Tests/Cpu/Tester/Instructions.cs
index 8b1b010f..25873718 100644
--- a/Ryujinx.Tests/Cpu/Tester/Instructions.cs
+++ b/Ryujinx.Tests/Cpu/Tester/Instructions.cs
@@ -5075,6 +5075,210 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result);
}
+ // sqdmulh_advsimd_vec.html#SQDMULH_asisdsame_only
+ public static void Sqdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
+ {
+ const bool U = false;
+
+ /* Decode Scalar */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+ int m = (int)UInt(Rm);
+
+ /* if size == '11' || size == '00' then ReservedValue(); */
+
+ int esize = 8 << (int)UInt(size);
+ int datasize = esize;
+ int elements = 1;
+
+ bool rounding = (U == true);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits result = new Bits(datasize);
+ Bits operand1 = V(datasize, n);
+ Bits operand2 = V(datasize, m);
+ BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
+ BigInteger element1;
+ BigInteger element2;
+ BigInteger product;
+ bool sat;
+
+ for (int e = 0; e <= elements - 1; e++)
+ {
+ element1 = SInt(Elem(operand1, e, esize));
+ element2 = SInt(Elem(operand2, e, esize));
+
+ product = (2 * element1 * element2) + round_const;
+
+ (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
+ Elem(result, e, esize, _result);
+ sat = _sat;
+
+ if (sat)
+ {
+ /* FPSR.QC = '1'; */
+ FPSR[27] = true; // TODO: Add named fields.
+ }
+ }
+
+ V(d, result);
+ }
+
+ // sqdmulh_advsimd_vec.html#SQDMULH_asimdsame_only
+ public static void Sqdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+ {
+ const bool U = false;
+
+ /* Decode Vector */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+ int m = (int)UInt(Rm);
+
+ /* if size == '11' || size == '00' then ReservedValue(); */
+
+ int esize = 8 << (int)UInt(size);
+ int datasize = (Q ? 128 : 64);
+ int elements = datasize / esize;
+
+ bool rounding = (U == true);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits result = new Bits(datasize);
+ Bits operand1 = V(datasize, n);
+ Bits operand2 = V(datasize, m);
+ BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
+ BigInteger element1;
+ BigInteger element2;
+ BigInteger product;
+ bool sat;
+
+ for (int e = 0; e <= elements - 1; e++)
+ {
+ element1 = SInt(Elem(operand1, e, esize));
+ element2 = SInt(Elem(operand2, e, esize));
+
+ product = (2 * element1 * element2) + round_const;
+
+ (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
+ Elem(result, e, esize, _result);
+ sat = _sat;
+
+ if (sat)
+ {
+ /* FPSR.QC = '1'; */
+ FPSR[27] = true; // TODO: Add named fields.
+ }
+ }
+
+ V(d, result);
+ }
+
+ // sqrdmulh_advsimd_vec.html#SQRDMULH_asisdsame_only
+ public static void Sqrdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
+ {
+ const bool U = true;
+
+ /* Decode Scalar */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+ int m = (int)UInt(Rm);
+
+ /* if size == '11' || size == '00' then ReservedValue(); */
+
+ int esize = 8 << (int)UInt(size);
+ int datasize = esize;
+ int elements = 1;
+
+ bool rounding = (U == true);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits result = new Bits(datasize);
+ Bits operand1 = V(datasize, n);
+ Bits operand2 = V(datasize, m);
+ BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
+ BigInteger element1;
+ BigInteger element2;
+ BigInteger product;
+ bool sat;
+
+ for (int e = 0; e <= elements - 1; e++)
+ {
+ element1 = SInt(Elem(operand1, e, esize));
+ element2 = SInt(Elem(operand2, e, esize));
+
+ product = (2 * element1 * element2) + round_const;
+
+ (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
+ Elem(result, e, esize, _result);
+ sat = _sat;
+
+ if (sat)
+ {
+ /* FPSR.QC = '1'; */
+ FPSR[27] = true; // TODO: Add named fields.
+ }
+ }
+
+ V(d, result);
+ }
+
+ // sqrdmulh_advsimd_vec.html#SQRDMULH_asimdsame_only
+ public static void Sqrdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+ {
+ const bool U = true;
+
+ /* Decode Vector */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+ int m = (int)UInt(Rm);
+
+ /* if size == '11' || size == '00' then ReservedValue(); */
+
+ int esize = 8 << (int)UInt(size);
+ int datasize = (Q ? 128 : 64);
+ int elements = datasize / esize;
+
+ bool rounding = (U == true);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits result = new Bits(datasize);
+ Bits operand1 = V(datasize, n);
+ Bits operand2 = V(datasize, m);
+ BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
+ BigInteger element1;
+ BigInteger element2;
+ BigInteger product;
+ bool sat;
+
+ for (int e = 0; e <= elements - 1; e++)
+ {
+ element1 = SInt(Elem(operand1, e, esize));
+ element2 = SInt(Elem(operand2, e, esize));
+
+ product = (2 * element1 * element2) + round_const;
+
+ (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
+ Elem(result, e, esize, _result);
+ sat = _sat;
+
+ if (sat)
+ {
+ /* FPSR.QC = '1'; */
+ FPSR[27] = true; // TODO: Add named fields.
+ }
+ }
+
+ V(d, result);
+ }
+
// sqsub_advsimd.html#SQSUB_asisdsame_only
public static void Sqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
{
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-27 07:27:44 +0000