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authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2018-04-08 21:08:57 +0200
committergdkchan <gab.dark.100@gmail.com>2018-04-08 16:08:57 -0300
commit7acd0e01226d64d05b2675f6ae07507039a31835 (patch)
treed49e5897ce86d32ee05b8fd9ab06379eef9f449b /Ryujinx.Tests/Cpu
parent980691f36bd7f18b98b636a2ad389c943571877c (diff)
Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74)
* Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update CpuTestSimdArithmetic.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs
Diffstat (limited to 'Ryujinx.Tests/Cpu')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs47
1 files changed, 47 insertions, 0 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
index 7765253b..ba82be31 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
@@ -44,6 +44,53 @@ namespace Ryujinx.Tests.Cpu
Assert.AreEqual(Result1, ThreadState.V0.X1);
});
}
+
+ [Test, Description("fmul s6, s1, v0.s[2]")]
+ public void Fmul_Se([Random(10)] float A, [Random(10)] float B)
+ {
+ AThreadState ThreadState = SingleOpcode(0x5F809826, V1: new AVec { S0 = A }, V0: new AVec { S2 = B });
+
+ Assert.That(ThreadState.V6.S0, Is.EqualTo(A * B));
+ }
+
+ [Test, Description("frecpe v2.4s, v0.4s")]
+ public void Frecpe_V([Random(100)] float A)
+ {
+ AThreadState ThreadState = SingleOpcode(0x4EA1D802, V0: new AVec { S0 = A, S1 = A, S2 = A, S3 = A });
+
+ Assert.That(ThreadState.V2.S0, Is.EqualTo(1 / A));
+ Assert.That(ThreadState.V2.S1, Is.EqualTo(1 / A));
+ Assert.That(ThreadState.V2.S2, Is.EqualTo(1 / A));
+ Assert.That(ThreadState.V2.S3, Is.EqualTo(1 / A));
+ }
+
+ [Test, Description("frecpe d0, d1")]
+ public void Frecpe_S([Random(100)] double A)
+ {
+ AThreadState ThreadState = SingleOpcode(0x5EE1D820, V1: new AVec { D0 = A });
+
+ Assert.That(ThreadState.V0.D0, Is.EqualTo(1 / A));
+ }
+
+ [Test, Description("frecps v4.4s, v2.4s, v0.4s")]
+ public void Frecps_V([Random(10)] float A, [Random(10)] float B)
+ {
+ AThreadState ThreadState = SingleOpcode(0x4E20FC44, V2: new AVec { S0 = A, S1 = A, S2 = A, S3 = A },
+ V0: new AVec { S0 = B, S1 = B, S2 = B, S3 = B });
+
+ Assert.That(ThreadState.V4.S0, Is.EqualTo(2 - (A * B)));
+ Assert.That(ThreadState.V4.S1, Is.EqualTo(2 - (A * B)));
+ Assert.That(ThreadState.V4.S2, Is.EqualTo(2 - (A * B)));
+ Assert.That(ThreadState.V4.S3, Is.EqualTo(2 - (A * B)));
+ }
+
+ [Test, Description("frecps d0, d1, d2")]
+ public void Frecps_S([Random(10)] double A, [Random(10)] double B)
+ {
+ AThreadState ThreadState = SingleOpcode(0x5E62FC20, V1: new AVec { D0 = A }, V2: new AVec { D0 = B });
+
+ Assert.That(ThreadState.V0.D0, Is.EqualTo(2 - (A * B)));
+ }
[TestCase(0x3FE66666u, false, 0x40000000u)]
[TestCase(0x3F99999Au, false, 0x3F800000u)]