| Age | Commit message (Expand) | Author |
|---|
| 2023-02-09 | Replace unicorn bindings with Nuget package (#4378) | TSRBerry |
| 2023-01-22 | Arm64: Simplify TryEncodeBitMask and use for constants (#4328) | merry |
| 2023-01-17 | Implement support for page sizes > 4KB (#4252) | gdkchan |
| 2022-12-21 | Fix CPU FCVTN instruction implementation (slow path) (#4159) | gdkchan |
| 2022-11-20 | Use upstream unicorn for Ryujinx.Tests.Unicorn (#3771) | TSRBerry |
| 2022-10-23 | Ryujinx.Tests.Unicorn: Implement IDisposable (#3794) | merry |
| 2022-10-19 | A32: Implement VCVTT, VCVTB (#3710) | merry |
| 2022-09-20 | Fpsr and Fpcr freed. (#3701) | LDj3SNuD |
| 2022-09-13 | Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on b... | gdkchan |
| 2022-09-13 | Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695) | gdkchan |
| 2022-09-11 | Implement VRINT (vector) Arm32 NEON instructions (#3691) | gdkchan |
| 2022-09-09 | Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPAD... | gdkchan |
| 2022-08-18 | Removed unused usings. (#3593) | Nicholas Rodine |
| 2022-08-05 | Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544) | gdkchan |
| 2022-07-06 | Implement CPU FCVT Half <-> Double conversion variants (#3439) | gdkchan |
| 2022-05-31 | Refactor CPU interface to allow the implementation of other CPU emulators (#3... | gdkchan |
| 2022-05-02 | Support memory aliasing (#2954) | gdkchan |
| 2022-04-21 | T32: Implement load/store single (immediate) (#3186) | merry |
| 2022-03-11 | KThread: Fix GetPsr mask (#3180) | merry |
| 2022-03-06 | T32: Implement Data Processing (Modified Immediate) instructions (#3178) | merry |
| 2022-03-05 | A32: Fix ALU immediate instructions (#3179) | merry |
| 2022-03-04 | T32: Implement B, B.cond, BL, BLX (#3155) | merry |
| 2022-02-22 | T32: Implement ALU (shifted register) instructions (#3135) | merry |
| 2022-02-17 | ARMeilleure: Thumb support (All T16 instructions) (#3105) | merry |
| 2022-02-08 | ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089) | merry |
| 2022-02-06 | ARMeilleure: A32: Implement SHADD8 (#3086) | merry |
| 2022-01-19 | Implement FCVTNS (Scalar GP) (#2953) | sharmander |
| 2022-01-04 | CPU - Implement FCVTMS (Vector) (#2937) | sharmander |
| 2021-12-08 | Implement UHADD8 instruction (#2908) | Piyachet Kanda |
| 2021-06-23 | Implement VORN (register) Arm32 instruction (#2396) | gdkchan |
| 2021-05-29 | Add multi-level function table (#2228) | FICTURE7 |
| 2021-05-24 | POWER - Performance Optimizations With Extensive Ramifications (#2286) | riperiperi |
| 2021-03-25 | Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139) | LDj3SNuD |
| 2021-02-22 | Implement VCNT instruction (#1963) | mageven |
| 2021-01-20 | CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests... | LDj3SNuD |
| 2021-01-04 | CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian... | LDj3SNuD |
| 2020-12-17 | Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow... | LDj3SNuD |
| 2020-12-16 | CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776) | sharmander |
| 2020-12-15 | CPU: Implement VFMA (Vector) (#1762) | sharmander |
| 2020-12-07 | CPU: Implement VFNMA.F32 | F.64 (#1783) | sharmander |
| 2020-12-07 | Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (... | LDj3SNuD |
| 2020-12-03 | CPU: Implement VFNMS.F32/64 (#1758) | sharmander |
| 2020-11-18 | CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & F... | LDj3SNuD |
| 2020-11-17 | shader cache: Fix Linux boot issues (#1709) | Mary |
| 2020-08-31 | CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492) | LDj3SNuD |
| 2020-08-13 | Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471) | LDj3SNuD |
| 2020-08-08 | CPU: This PR fixes Fpscr, among other things. (#1433) | LDj3SNuD |
| 2020-07-19 | Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192) | Valentin PONS |
| 2020-07-17 | CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394) | LDj3SNuD |
| 2020-07-17 | CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390) | LDj3SNuD |
