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| author | gdkchan <gab.dark.100@gmail.com> | 2022-09-13 19:51:40 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-13 19:51:40 -0300 |
| commit | 8e119a1e9694416289c4c4c7ed38c408c096f9a2 (patch) | |
| tree | 76e7dd37606858a91d9400824da798448cb6d41f /Ryujinx.Tests/Cpu | |
| parent | e05bf90af600f5c75a13a0b4113b7fc6a641ff6a (diff) | |
Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)
Diffstat (limited to 'Ryujinx.Tests/Cpu')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTest32.cs | 4 | ||||
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestAlu32.cs | 56 |
2 files changed, 41 insertions, 19 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTest32.cs b/Ryujinx.Tests/Cpu/CpuTest32.cs index 1bd87aee..be8df8df 100644 --- a/Ryujinx.Tests/Cpu/CpuTest32.cs +++ b/Ryujinx.Tests/Cpu/CpuTest32.cs @@ -456,6 +456,10 @@ namespace Ryujinx.Tests.Cpu Assert.Multiple(() => { + Assert.That(_context.GetPstateFlag(PState.GE0Flag), Is.EqualTo((_unicornEmu.CPSR & (1u << 16)) != 0), "GE0Flag"); + Assert.That(_context.GetPstateFlag(PState.GE1Flag), Is.EqualTo((_unicornEmu.CPSR & (1u << 17)) != 0), "GE1Flag"); + Assert.That(_context.GetPstateFlag(PState.GE2Flag), Is.EqualTo((_unicornEmu.CPSR & (1u << 18)) != 0), "GE2Flag"); + Assert.That(_context.GetPstateFlag(PState.GE3Flag), Is.EqualTo((_unicornEmu.CPSR & (1u << 19)) != 0), "GE3Flag"); Assert.That(_context.GetPstateFlag(PState.QFlag), Is.EqualTo(_unicornEmu.QFlag), "QFlag"); Assert.That(_context.GetPstateFlag(PState.VFlag), Is.EqualTo(_unicornEmu.OverflowFlag), "VFlag"); Assert.That(_context.GetPstateFlag(PState.CFlag), Is.EqualTo(_unicornEmu.CarryFlag), "CFlag"); diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs index f04aa22e..c7537cd9 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs @@ -10,6 +10,21 @@ namespace Ryujinx.Tests.Cpu #if Alu32 #region "ValueSource (Opcodes)" + private static uint[] _SU_H_AddSub_8_() + { + return new uint[] + { + 0xe6100f90u, // SADD8 R0, R0, R0 + 0xe6100ff0u, // SSUB8 R0, R0, R0 + 0xe6300f90u, // SHADD8 R0, R0, R0 + 0xe6300ff0u, // SHSUB8 R0, R0, R0 + 0xe6500f90u, // UADD8 R0, R0, R0 + 0xe6500ff0u, // USUB8 R0, R0, R0 + 0xe6700f90u, // UHADD8 R0, R0, R0 + 0xe6700ff0u // UHSUB8 R0, R0, R0 + }; + } + private static uint[] _Ssat_Usat_() { return new uint[] @@ -150,15 +165,14 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise] - public void Uhadd8([Values(0u, 0xdu)] uint rd, - [Values(1u)] uint rm, - [Values(2u)] uint rn, - [Random(RndCnt)] uint w0, - [Random(RndCnt)] uint w1, - [Random(RndCnt)] uint w2) + public void SU_H_AddSub_8([ValueSource("_SU_H_AddSub_8_")] uint opcode, + [Values(0u, 0xdu)] uint rd, + [Values(1u)] uint rm, + [Values(2u)] uint rn, + [Random(RndCnt)] uint w0, + [Random(RndCnt)] uint w1, + [Random(RndCnt)] uint w2) { - uint opcode = 0xE6700F90u; // UHADD8 R0, R0, R0 - opcode |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rn & 15) << 16); uint sp = TestContext.CurrentContext.Random.NextUInt(); @@ -169,20 +183,24 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise] - public void Uhsub8([Values(0u, 0xdu)] uint rd, - [Values(1u)] uint rm, - [Values(2u)] uint rn, - [Random(RndCnt)] uint w0, - [Random(RndCnt)] uint w1, - [Random(RndCnt)] uint w2) + public void Uadd8_Sel([Values(0u)] uint rd, + [Values(1u)] uint rm, + [Values(2u)] uint rn, + [Random(RndCnt)] uint w0, + [Random(RndCnt)] uint w1, + [Random(RndCnt)] uint w2) { - uint opcode = 0xE6700FF0u; // UHSUB8 R0, R0, R0 + uint opUadd8 = 0xE6500F90; // UADD8 R0, R0, R0 + uint opSel = 0xE6800FB0; // SEL R0, R0, R0 - opcode |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rn & 15) << 16); + opUadd8 |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rn & 15) << 16); + opSel |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rn & 15) << 16); - uint sp = TestContext.CurrentContext.Random.NextUInt(); - - SingleOpcode(opcode, r0: w0, r1: w1, r2: w2, sp: sp); + SetContext(r0: w0, r1: w1, r2: w2); + Opcode(opUadd8); + Opcode(opSel); + Opcode(0xE12FFF1E); // BX LR + ExecuteOpcodes(); CompareAgainstUnicorn(); } |