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| author | sharmander <saldabain.dev@gmail.com> | 2020-12-14 22:01:52 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-15 00:01:52 -0300 |
| commit | 3332b29f01993d22195f417d39ae4074d53fb55c (patch) | |
| tree | f573fb1e8113fd3359d97e99b7d9cdebef4265af /Ryujinx.Tests/Cpu | |
| parent | 47ba81c661c7ccd8bf2c972b73ad444cbf0d9744 (diff) | |
CPU: Implement VFMA (Vector) (#1762)
* Implement VFMA.F64
* Simplify switch
* Simplify FMA Instructions into their own IntrinsicType.
* Remove whitespace
* Fix indentation
* Change tests for Vfnms -- disable inf / nan
* Move args up, not description ;)
* Implementation Complete.
All Tests Pass (Slow / Fast Path)
* Move location of function in assembler + test updates.
* Shift params upwards
* Remove unused function
* Update PTC version.
* Add comments / re-oreder opcode table.
* Remove whitespace
* Fix nit
* Fix nit.
* Fix whitespace
* Wrong opcode was used by a bad merge.
* Addressed rip's comments.
Diffstat (limited to 'Ryujinx.Tests/Cpu')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs index dc5903d5..4298bd1f 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs @@ -293,6 +293,52 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Nzcv); } + [Test, Pairwise, Description("VFMA.F<size> <Vd>, <Vn>, <Vm>")] + public void Vfma([Values(0u, 1u)] uint rd, + [Values(0u, 1u)] uint rn, + [Values(0u, 1u)] uint rm, + [Values(0u, 1u)] uint Q, + [ValueSource("_2S_F_")] ulong z, + [ValueSource("_2S_F_")] ulong a, + [ValueSource("_2S_F_")] ulong b ) + { + uint opcode = 0xf2000c10; + + V128 v0; + V128 v1; + V128 v2; + + uint c = (uint) BitConverter.SingleToInt32Bits(z); + uint d = (uint) BitConverter.SingleToInt32Bits(a); + uint e = (uint) BitConverter.SingleToInt32Bits(b); + if (Q == 0) + { + opcode |= (((rm & 0x1) << 5) | (rm & 0x1e) >> 1); + opcode |= (((rd & 0x1) << 22) | (rd & 0x1e) << 11); + opcode |= (((rn & 0x1) << 7) | (rn & 0x1e) >> 15); + + v0 = MakeVectorE0E1(c, c); + v1 = MakeVectorE0E1(d, c); + v2 = MakeVectorE0E1(e, c); + } + else + { + rd = rn = rm = 0; // Needed, as these values cannot be odd values if Q == 1. + opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0); + opcode |= (((rd & 0x10) << 18) | (rd & 0xf) << 12); + opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16); + + v0 = MakeVectorE0E1E2E3(c, c, d, e); + v1 = MakeVectorE0E1E2E3(d, c, e, c); + v2 = MakeVectorE0E1E2E3(e, c, d, c); + } + + opcode |= ((Q & 1) << 6); + + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2); + CompareAgainstUnicorn(); + } + [Test, Pairwise, Description("VFNMA.F<size> <Vd>, <Vn>, <Vm>")] public void Vfnma([Values(0u, 1u)] uint rd, [Values(0u, 1u)] uint rn, |