diff options
| author | sharmander <saldabain.dev@gmail.com> | 2020-12-03 14:20:02 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-03 20:20:02 +0100 |
| commit | b479a43939b77b7f6d67f103f1fdc9126466f780 (patch) | |
| tree | b1655fc5a2e40e6bb4d93179d4d1e0f70db44eed /Ryujinx.Tests/Cpu | |
| parent | c00d39b675d0ebf7ebf5be1135addbbee2510d93 (diff) | |
CPU: Implement VFNMS.F32/64 (#1758)
* Add necessary methods / op-code
* Enable Support for FMA Instruction Set
* Add Intrinsics / Assembly Opcodes for VFMSUB231XX.
* Add X86 Instructions for VFMSUB231XX
* Implement VFNMS
* Implement VFNMS Tests
* Add special cases for FMA instructions.
* Update PPTC Version
* Remove unused Op
* Move Check into Assert / Cleanup
* Rename and cleanup
* Whitespace
* Whitespace / Rename
* Re-sort
* Address final requests
* Implement VFMA.F64
* Simplify switch
* Simplify FMA Instructions into their own IntrinsicType.
* Remove whitespace
* Fix indentation
* Change tests for Vfnms -- disable inf / nan
* Move args up, not description ;)
* Undo vfma
* Completely remove vfms code.,
* Fix order of instruction in assembler
Diffstat (limited to 'Ryujinx.Tests/Cpu')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | 39 |
1 files changed, 37 insertions, 2 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs index 92ad329f..1b9b38ab 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs @@ -184,8 +184,8 @@ namespace Ryujinx.Tests.Cpu private const int RndCnt = 2; private static readonly bool NoZeros = false; - private static readonly bool NoInfs = false; - private static readonly bool NoNaNs = false; + private static readonly bool NoInfs = true; + private static readonly bool NoNaNs = true; [Explicit] [Test, Pairwise, Description("VADD.f32 V0, V0, V0")] @@ -293,6 +293,41 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Nzcv); } + [Test, Pairwise, Description("VFNMS.F<size> <Vd>, <Vn>, <Vm>")] + public void Vfnms([Values(0u, 1u)] uint rd, + [Values(0u, 1u)] uint rn, + [Values(0u, 1u)] uint rm, + [Values(2u, 3u)] uint size, + [ValueSource("_2S_F_")] ulong z, + [ValueSource("_2S_F_")] ulong a, + [ValueSource("_2S_F_")] ulong b) + { + uint opcode = 0xee900a00; + + if (size == 2) + { + opcode |= (((rm & 0x1) << 5) | (rm & 0x1e) >> 1); + opcode |= (((rd & 0x1) << 22) | (rd & 0x1e) << 11); + opcode |= (((rn & 0x1) << 7) | (rn & 0x1e) >> 15); + + } + else + { + opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0); + opcode |= (((rd & 0x10) << 18) | (rd & 0xf) << 12); + opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16); + } + + opcode |= ((size & 3) << 8); + + V128 v0 = MakeVectorE0E1(z, z); + V128 v1 = MakeVectorE0E1(a, z); + V128 v2 = MakeVectorE0E1(b, z); + + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2); + CompareAgainstUnicorn(); + } + [Test, Pairwise, Description("VMLSL.<type><size> <Vd>, <Vn>, <Vm>")] public void Vmlsl_I([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, |