| Age | Commit message (Expand) | Author |
|---|
| 2018-10-30 | Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) | Alex Barney |
| 2018-10-23 | Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. ... | LDj3SNuD |
| 2018-09-26 | Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Sca... | gdkchan |
| 2018-09-01 | Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_... | LDj3SNuD |
| 2018-07-14 | Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225) | gdkchan |
| 2018-07-12 | AInstEmitSimdCvt: Half-precision to single-precision conversion (#235) | Merry |
| 2018-05-18 | Add scalar variants of FCVTZS/FCVTZU, fix a issue on Ryushader | gdkchan |
| 2018-05-11 | Add intrinsics support (#121) | gdkchan |
| 2018-03-05 | Add MUL (vector by element), fix FCVTN, make svcs use MakeError too | gdkchan |
| 2018-03-05 | Add FCVTL and FCVTN instruction (no Half support yet), stub SvcClearEvent | gdkchan |
| 2018-02-23 | Map heap on heap base region, fix for thread start on homebrew, add FCVTMU an... | gdkchan |
| 2018-02-20 | Split main project into core,graphics and chocolarm4 subproject (#29) | emmauss |
