diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-09-01 16:52:51 +0200 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-09-01 11:52:51 -0300 |
| commit | 42e4e02a648812c4dee1574a5cd9e7dddf7b2458 (patch) | |
| tree | e5d4992e36bf17255d82690388ff4d185faf676f /ChocolArm64/Instruction/AInstEmitSimdCvt.cs | |
| parent | 326777ca4a68b38c7a5e44c76291f09f07ddcf2e (diff) | |
Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)
* Update AOpCodeTable.cs
* Update AInstEmitSimdCvt.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Add QCFlagBit.
* Add QCFlagBit.
Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdCvt.cs')
| -rw-r--r-- | ChocolArm64/Instruction/AInstEmitSimdCvt.cs | 70 |
1 files changed, 69 insertions, 1 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs index 7b355494..231de0af 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs @@ -106,6 +106,26 @@ namespace ChocolArm64.Instruction } } + public static void Fcvtns_S(AILEmitterCtx Context) + { + EmitFcvtn(Context, Signed: true, Scalar: true); + } + + public static void Fcvtns_V(AILEmitterCtx Context) + { + EmitFcvtn(Context, Signed: true, Scalar: false); + } + + public static void Fcvtnu_S(AILEmitterCtx Context) + { + EmitFcvtn(Context, Signed: false, Scalar: true); + } + + public static void Fcvtnu_V(AILEmitterCtx Context) + { + EmitFcvtn(Context, Signed: false, Scalar: false); + } + public static void Fcvtps_Gp(AILEmitterCtx Context) { EmitFcvt_s_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Ceiling))); @@ -250,6 +270,54 @@ namespace ChocolArm64.Instruction } } + private static void EmitFcvtn(AILEmitterCtx Context, bool Signed, bool Scalar) + { + AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; + + int SizeF = Op.Size & 1; + int SizeI = SizeF + 2; + + int Bytes = Op.GetBitsCount() >> 3; + int Elems = !Scalar ? Bytes >> SizeI : 1; + + if (Scalar && (SizeF == 0)) + { + EmitVectorZeroLowerTmp(Context); + } + + for (int Index = 0; Index < Elems; Index++) + { + EmitVectorExtractF(Context, Op.Rn, Index, SizeF); + + EmitRoundMathCall(Context, MidpointRounding.ToEven); + + if (SizeF == 0) + { + AVectorHelper.EmitCall(Context, Signed + ? nameof(AVectorHelper.SatF32ToS32) + : nameof(AVectorHelper.SatF32ToU32)); + + Context.Emit(OpCodes.Conv_U8); + } + else /* if (SizeF == 1) */ + { + AVectorHelper.EmitCall(Context, Signed + ? nameof(AVectorHelper.SatF64ToS64) + : nameof(AVectorHelper.SatF64ToU64)); + } + + EmitVectorInsertTmp(Context, Index, SizeI); + } + + Context.EmitLdvectmp(); + Context.EmitStvec(Op.Rd); + + if ((Op.RegisterSize == ARegisterSize.SIMD64) || Scalar) + { + EmitVectorZeroUpper(Context, Op.Rd); + } + } + private static void EmitFcvt_s_Gp(AILEmitterCtx Context, Action Emit) { EmitFcvt___Gp(Context, Emit, true); @@ -569,4 +637,4 @@ namespace ChocolArm64.Instruction } } } -}
\ No newline at end of file +} |
