aboutsummaryrefslogtreecommitdiff
path: root/src/video_core/command_processor.cpp
AgeCommit message (Collapse)Author
2018-12-03Removed unused file.Subv
This is a leftover from #1792
2018-11-17gl_rasterizer: Skip VB upload if the state is clean.Markus Wick
2018-10-30global: Use std::optional instead of boost::optional (#1578)Frederic L
* get rid of boost::optional * Remove optional references * Use std::reference_wrapper for optional references * Fix clang format * Fix clang format part 2 * Adressed feedback * Fix clang format and MacOS build
2018-09-12GPU: Basic implementation of the Kepler Inline Memory engine (p2mf).Subv
This engine writes data from a FIFO register into the configured address.
2018-09-10video_core: Refactor command_processor.Markus Wick
Inline the WriteReg helper as it is called ~20k times per frame.
2018-09-10video_core: Move command buffer loop.Markus Wick
This moves the hot loop into video_core. This refactoring shall reduce the CPU overhead of calling ProcessCommandList.
2018-09-04command_processor: Use std::array for bound_engines.Markus Wick
subchannel is a 3 bit field. So there must not be more than 8 bound engines. And using a hashmap for up to 8 values is a bit overpowered.
2018-08-07Lowered down the logging for methodsHexagon12
2018-07-02Update clang formatJames Rowe
2018-07-02Rename logging macro back to LOG_*James Rowe
2018-06-12GPU: Partially implemented the Maxwell DMA engine.Subv
Only tiled->linear and linear->tiled copies that aren't offsetted are supported for now. Queries are not supported. Swizzled copies are not supported.
2018-05-24GPU: Allow command lists to rebind a channel to another engine in the middle ↵Subv
of the command list.
2018-04-25GPU: Move the Maxwell3D macro uploading code to the inside of the Maxwell3D ↵Subv
processor. It doesn't belong in the PFIFO handler.
2018-04-25GPU: Corrected the upper bound of the PFIFO method ids in the command processor.Subv
2018-04-25video-core: Move logging macros over to new fmt-capable onesLioncash
2018-04-24memory_manager: Make GpuToCpuAddress return an optional.bunnei
2018-04-24memory_manager: Use GPUVAdddr, not PAddr, for GPU addresses.bunnei
2018-03-18GPU: Store uploaded GPU macros and keep track of the number of method ↵Subv
parameters.
2018-03-18GPU: Macros are specific to the Maxwell3D engine, so handle them internally.Subv
2018-03-16GPU: Process command mode 5 (IncreaseOnce) differently from other commands.Subv
Accumulate all arguments before calling the desired method. Note: Maybe we should do the same for the NonIncreasing mode?
2018-02-11Make a GPU class in VideoCore to contain the GPU state.Subv
Also moved the GPU MemoryManager class to video_core since it makes more sense for it to be there.
2018-02-11GPU: Added a command processor to decode the GPU pushbuffers and forward the ↵Subv
commands to their respective engines.
2018-01-12Remove references to PICA and rasterizers in video_coreJames Rowe
2017-10-14hle: Initial implementation of NX service framework and IPC.bunnei
2017-10-04Extracted the attribute setup and draw commands into their own functionsHuw Pascoe
2017-09-23Remove pipeline.gpu_mode and fix minor issuesJames Rowe
2017-09-11GPU: Add draw for immediate and batch modesJames Rowe
PR #1461 introduced a regression where some games would change configuration even while in the poorly named "drawing" mode, which broke the heuristic citra was using to determine when to draw the batch. This change adds back in a draw call for batching, and also adds in a draw call in immediate mode each time it adds a triangle.
2017-08-19pica/command_processor: build geometry pipeline and run geometry shaderwwylele
The geometry pipeline manages data transfer between VS, GS and primitive assembler. It has known four modes: - no GS mode: sends VS output directly to the primitive assembler (what citra currently does) - GS mode 0: sends VS output to GS input registers, and sends GS output to primitive assembler - GS mode 1: sends VS output to GS uniform registers, and sends GS output to primitive assembler. It also takes an index from the index buffer at the beginning of each primitive for determine the primitive size. - GS mode 2: similar to mode 1, but doesn't take the index and uses a fixed primitive size. hwtest shows that immediate mode also supports GS (at least for mode 0), so the geometry pipeline gets refactored into its own class for supporting both drawing mode. In the immediate mode, some games don't set the pipeline registers to a valid value until the first attribute input, so a geometry pipeline reset flag is set in `pipeline.vs_default_attributes_setup.index` trigger, and the actual pipeline reconfigure is triggered in the first attribute input. In the normal drawing mode with index buffer, the vertex cache is a little bit modified to support the geometry pipeline. Instead of OutputVertex, it now holds AttributeBuffer, which is the input to the geometry pipeline. The AttributeBuffer->OutputVertex conversion is done inside the pipeline vertex handler. The actual hardware vertex cache is believed to be implemented in a similar way (because this is the only way that makes sense). Both geometry pipeline and GS unit rely on states preservation across drawing call, so they are put into the global state. In the future, the other three vertex shader units should be also placed in the global state, and a scheduler should be implemented on top of the four units. Note that the current gs_unit already allows running VS on it in the future.
2017-08-07pica: upload shared shader code to both unitwwylele
2017-05-24Merge pull request #2697 from wwylele/proctexYuri Kunde Schlesner
Implemented Procedural Texture (Texture Unit 3)
2017-05-20pica/swrasterizer: implement procedural texturewwylele
2017-05-17pica: use correct register value for shader bool_uniformswwylele
variable value is not masked. the masked and combined register value should be used instead
2017-05-12Pica: Write GS registersJannik Vogel
This adds the handlers for the geometry shader register writes which will call the functions from the previous commit to update registers for the GS.
2017-05-12Pica: Write shader registers in functionsJannik Vogel
The commit after this one adds GS register writes, so this moves the VS handlers into functions so they can be re-used and extended more easily.
2017-02-09VideoCore: Split regs.h inclusionsYuri Kunde Schlesner
2017-02-08VideoCore: Use union to index into Regs structYuri Kunde Schlesner
Also remove some unused members.
2017-02-04VideoCore: Move Regs to its own fileYuri Kunde Schlesner
2017-02-04VideoCore: Split geometry pipeline regs from Regs structYuri Kunde Schlesner
2017-02-04VideoCore: Split texturing regs from Regs structYuri Kunde Schlesner
2017-02-04VideoCore: Split rasterizer regs from Regs structYuri Kunde Schlesner
2017-01-29VideoCore: Split shader output writing from semantic loadingYuri Kunde Schlesner
2017-01-29VideoCore: Consistently use shader configuration to load attributesYuri Kunde Schlesner
2017-01-29VideoCore: Use correct register for immediate mode attribute countYuri Kunde Schlesner
2017-01-29VideoCore: Rename some types to more accurate namesYuri Kunde Schlesner
2017-01-29VideoCore: Change misleading register namesYuri Kunde Schlesner
A few registers had names such as "count" or "number" when they actually contained the maximum (that is, count - 1). This can easily lead to hard to notice off by one errors.
2017-01-25VideoCore/Shader: Move entry_point to SetupBatchYuri Kunde Schlesner
2017-01-25VideoCore/Shader: Move per-batch ShaderEngine state into ShaderSetupYuri Kunde Schlesner
2017-01-25Shader: Remove OutputRegisters structYuri Kunde Schlesner
2017-01-25VideoCore/Shader: Split shader uniform state and shader engineYuri Kunde Schlesner
Currently there's only a single dummy implementation, which will be split in a following commit.
2017-01-25VideoCore/Shader: Use only entry_point as ShaderSetup paramYuri Kunde Schlesner
This removes all implicit dependency of ShaderState on global PICA state.
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-09 03:51:48 +0000