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path: root/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
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2018-10-30Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)Alex Barney
* Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment
2018-10-25Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, ↵LDj3SNuD
S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480) * Update AILEmitterCtx.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdShift.cs
2018-10-23Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. ↵LDj3SNuD
(full FP emu.). Add 4 FP Tests. (#468) * Update CpuTest.cs * Update CpuTestSimd.cs * Superseded. * Update AInstEmitSimdCvt.cs * Update ASoftFloat.cs * Nit. * Update PackageReferences. * Update AInstEmitSimdArithmetic.cs * Update AVectorHelper.cs * Update ASoftFloat.cs * Update ASoftFallback.cs * Update AThreadState.cs * Create FPType.cs * Create FPExc.cs * Create FPCR.cs * Create FPSR.cs * Update ARoundMode.cs * Update APState.cs * Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover. * Nits.
2018-10-13Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, ↵LDj3SNuD
S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449) * Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdShift.cs * Update ASoftFallback.cs * Update ASoftFloat.cs * Update AOpCodeSimdRegElemF.cs * Update CpuTestSimdIns.cs * Update CpuTestSimdRegElem.cs * Create CpuTestSimdRegElemF.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Superseded Fmul_Se Test. Nit. * Address PR feedback. * Address PR feedback. * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update AInstEmitSimdShift.cs
2018-10-05Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437)LDj3SNuD
* Update CpuTest.cs * Delete CpuTestSimdCmp.cs Obsolete. * Update CpuTestSimdArithmetic.cs Superseded. * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update ASoftFloat.cs * Nit. * Update AOpCodeTable.cs * Update AOptimizations.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFloat.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFloat.cs * Update CpuTestSimdReg.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFloat.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs
2018-09-26Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT ↵gdkchan
(Scalar) using SSE intrinsics (#405) * Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements * Remove useless space * Address PR feedback * Revert EmitVectorZero32_128 changes
2018-09-22Add FMAXP and FMINP (Vector) instructions on the CPU (#412)gdkchan
* Add FMAXP and FMINP (Vector) instructions on the CPU * Address PR feedback
2018-09-17Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; ↵LDj3SNuD
add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409) * Update AOpCodeTable.cs * Update AInstEmitSimdShift.cs * Update CpuTestSimdShImm.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Create CpuTestSimdIns.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs
2018-09-08Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)LDj3SNuD
* Update AOpCodeTable.cs * Update AInstEmitSimdShift.cs * Update ASoftFallback.cs * Update AOpCodeSimdShImm.cs * Update ABitUtils.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Create CpuTestSimdShImm.cs * Create CpuTestSimdRegElem.cs * Address PR feedback. * Nit. * Nit.
2018-09-01Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, ↵LDj3SNuD
Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390) * Update AOpCodeTable.cs * Update AInstEmitSimdCvt.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Add QCFlagBit. * Add QCFlagBit.
2018-08-27Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)LDj3SNuD
* Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdCrypto.cs
2018-08-14Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273)gdkchan
2018-08-13Add Sadalp_V, Saddlp_V, Uadalp_V, Uaddlp_V instructions; add 8 Tests. (#340)LDj3SNuD
* Update Instructions.cs * Update CpuTestSimd.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs
2018-08-10Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. ↵LDj3SNuD
Now all saturating methods are on ASoftFallback. (#334) * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update ASoftFallback.cs * Update CpuTestAlu.cs * Update CpuTestAluImm.cs * Update CpuTestAluRs.cs * Update CpuTestAluRx.cs * Update CpuTestBfm.cs * Update CpuTestCcmpImm.cs * Update CpuTestCcmpReg.cs * Update CpuTestCsel.cs * Update CpuTestMov.cs * Update CpuTestMul.cs * Update Ryujinx.Tests.csproj * Update Ryujinx.csproj * Update Luea.csproj * Update Ryujinx.ShaderTools.csproj * Address PR feedback (further tested). * Address PR feedback.
2018-08-05More accurate impl of FMINNM/FMAXNM, add vector variants (#296)gdkchan
* More accurate impl of FMINNM/FMAXNM, add vector variants * Optimize for the 0 case when op1 != op2 * Address PR feedback
2018-08-04Add SQADD, UQADD, SQSUB, UQSUB, SUQADD, USQADD, SQABS, SQNEG (Scalar, ↵LDj3SNuD
Vector) instructions; add 24 Tests. Most saturation instructions now on ASoftFallback. (#314) * Update AOpCodeTable.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdArithmetic.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdHelper.cs * Update ASoftFallback.cs * Update AInstEmitSimdHelper.cs * Update ASoftFallback.cs * Update AInstEmitSimdHelper.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update ASoftFallback.cs * Update AInstEmitSimdHelper.cs * Opt. (retest).
2018-07-18Implement Ssubw_V and Usubw_V instructions. (#287)LDj3SNuD
* Update AOpCodeTable.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdMove.cs * Update AInstEmitSimdCmp.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs
2018-07-15Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& ↵LDj3SNuD
Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268) * Update CpuTestSimdArithmetic.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update Instructions.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdMove.cs * Delete CpuTestSimdMove.cs
2018-07-14Improve CountLeadingZeros() algorithm, nits. (#219)LDj3SNuD
* Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update ASoftFallback.cs * Update ASoftFallback.cs * Update AInstEmitSimdArithmetic.cs
2018-07-14Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)gdkchan
* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions * Address PR feedback * Address PR feedback * Remove another useless temp var * nit: Alignment * Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount() * Fix encodings and move flag bit test out of the loop
2018-07-08ChocolArm64: More accurate implementation of Frecpe & Frecps (#228)Merry
* ChocolArm64: More accurate implementation of Frecpe * ChocolArm64: Handle infinities and zeros in Frecps
2018-07-03Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions (#200)gdkchan
2018-07-03Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). ↵LDj3SNuD
Improve CountSetBits8() algorithm. (#212) * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdLogical.cs * Update AVectorHelper.cs * Update ASoftFallback.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Improve CountSetBits8() algorithm. * Improve CountSetBits8() algorithm.
2018-06-30Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, ↵LDj3SNuD
Uabdl_V. Add 16 tests. (#204) * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update Instructions.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs
2018-06-28Add support for the FMLA (by element/scalar) instruction (#187)gdkchan
* Add support for the FMLA (by element/scalar) instruction * Fix encoding
2018-06-25Add Sqxtun_S, Sqxtun_V with 3 tests. (#188)LDj3SNuD
* Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimd.cs
2018-06-25Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, ↵LDj3SNuD
Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183) * Add files via upload * Add files via upload * Add files via upload * CPE * Add EmitSse42Crc32() * Update CpuTestSimdCmp.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update Instructions.cs
2018-06-25Add opcodes SQXTUN_S and SQXTUN_V (#184)Rygnus
* Add SQXTUN_S and SQXTUN_V Part 1/2 of commit * Add SQXTUN_S and SQXTUN_V (2/2) Part 2/2 of commit
2018-06-18Add the FADDP (scalar) instructiongdkchan
2018-06-12Implement Fabs_V (#146)Lordmau5
2018-05-11Add intrinsics support (#121)gdkchan
* Initial intrinsics support * Update tests to work with the new Vector128 type and intrinsics * Drop SSE4.1 requirement * Fix copy-paste mistake
2018-04-29Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). (#110)LDj3SNuD
* Update ILGeneratorEx.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update Pseudocode.cs * Update Instructions.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdArithmetic.cs
2018-04-25Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, ↵LDj3SNuD
Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104) * Update AOpCodeTable.cs * Update AInstEmitSimdLogical.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs
2018-04-20Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 ↵LDj3SNuD
Tests. (#92) * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Pseudocode.cs * Update Instructions.cs * Update Bits.cs * Create CpuTestSimd.cs * Create CpuTestSimdReg.cs * Update CpuTestSimd.cs Provide a better supply of input values for the 20 Simd Tests. * Update CpuTestSimdReg.cs Provide a better supply of input values for the 20 Simd Tests. * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs
2018-04-19Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89)MS-DOS1999
2018-04-18Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. (#88)LDj3SNuD
* Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AOpCodeTable.cs
2018-04-08Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & ↵LDj3SNuD
vector) instructions. Add 5 simple tests. (#74) * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update CpuTestSimdArithmetic.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs
2018-04-06Fix FRSQRTS and FCM* (scalar) instructionsgdkchan
2018-04-06Add FMLS (vector) instructiongdkchan
2018-04-05Add FRSQRTS and FCM* instructionsgdkchan
2018-04-05Implement Frsqrte_S (#72)Merry
* Implement Frsqrte_S * Implement Frsqrte_V * Add Frsqrte_S test
2018-04-04Add Faddp (vector) instructiongdkchan
2018-04-04Add FNEG (vector) instructiongdkchan
2018-03-30Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD ↵gdkchan
(it shouldn't accumulate, this is another variation of the instruction)
2018-03-30Add UABD instructiongdkchan
2018-03-30Add UABDL instructiongdkchan
2018-03-30Add UADDL instructiongdkchan
2018-03-30Add UHADD instructiongdkchan
2018-03-24Add FNMADD instructiongdkchan
2018-03-23Add Frint Instructions and Tests (#62)MS-DOS1999
* add 'ADC 32bit and Overflow' test * Add WZR/WSP tests * fix ADC and ADDS * add ADCS test * add SBCS test * indent my code and delete comment * '/' <- i hate you x) * remove spacebar char * remove false tab * add frintx_S test * update frintx_S test * add ASRV test * fix new line * fix PR * fix indent * Add add_V tests * work on Frintx_V * Add Frintx_V Instruction * add some instruction and test * Syntax + indent * Delete Console Write * Delete Console Write 2 * CR del * Skip NaNs tests * Skip NaNs tests 2 * Fix errors 1 * Fix errors 2
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