diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-09-01 16:52:51 +0200 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-09-01 11:52:51 -0300 |
| commit | 42e4e02a648812c4dee1574a5cd9e7dddf7b2458 (patch) | |
| tree | e5d4992e36bf17255d82690388ff4d185faf676f /ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs | |
| parent | 326777ca4a68b38c7a5e44c76291f09f07ddcf2e (diff) | |
Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)
* Update AOpCodeTable.cs
* Update AInstEmitSimdCvt.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Add QCFlagBit.
* Add QCFlagBit.
Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs')
| -rw-r--r-- | ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs index 1e4002a0..a291a7e5 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs @@ -1032,6 +1032,11 @@ namespace ChocolArm64.Instruction EmitAddLongPairwise(Context, Signed: true, Accumulate: true); } + public static void Saddl_V(AILEmitterCtx Context) + { + EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add)); + } + public static void Saddlp_V(AILEmitterCtx Context) { EmitAddLongPairwise(Context, Signed: true, Accumulate: false); @@ -1217,6 +1222,11 @@ namespace ChocolArm64.Instruction }); } + public static void Ssubl_V(AILEmitterCtx Context) + { + EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub)); + } + public static void Ssubw_V(AILEmitterCtx Context) { EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub)); @@ -1391,6 +1401,24 @@ namespace ChocolArm64.Instruction EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo)); } + public static void Umlal_V(AILEmitterCtx Context) + { + EmitVectorWidenRnRmTernaryOpZx(Context, () => + { + Context.Emit(OpCodes.Mul); + Context.Emit(OpCodes.Add); + }); + } + + public static void Umlsl_V(AILEmitterCtx Context) + { + EmitVectorWidenRnRmTernaryOpZx(Context, () => + { + Context.Emit(OpCodes.Mul); + Context.Emit(OpCodes.Sub); + }); + } + public static void Umull_V(AILEmitterCtx Context) { EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul)); @@ -1450,6 +1478,11 @@ namespace ChocolArm64.Instruction EmitVectorSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate); } + public static void Usubl_V(AILEmitterCtx Context) + { + EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub)); + } + public static void Usubw_V(AILEmitterCtx Context) { EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub)); |