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path: root/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
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Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs')
-rw-r--r--ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs33
1 files changed, 33 insertions, 0 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
index 1e4002a0..a291a7e5 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
@@ -1032,6 +1032,11 @@ namespace ChocolArm64.Instruction
EmitAddLongPairwise(Context, Signed: true, Accumulate: true);
}
+ public static void Saddl_V(AILEmitterCtx Context)
+ {
+ EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
+ }
+
public static void Saddlp_V(AILEmitterCtx Context)
{
EmitAddLongPairwise(Context, Signed: true, Accumulate: false);
@@ -1217,6 +1222,11 @@ namespace ChocolArm64.Instruction
});
}
+ public static void Ssubl_V(AILEmitterCtx Context)
+ {
+ EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
+ }
+
public static void Ssubw_V(AILEmitterCtx Context)
{
EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
@@ -1391,6 +1401,24 @@ namespace ChocolArm64.Instruction
EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
}
+ public static void Umlal_V(AILEmitterCtx Context)
+ {
+ EmitVectorWidenRnRmTernaryOpZx(Context, () =>
+ {
+ Context.Emit(OpCodes.Mul);
+ Context.Emit(OpCodes.Add);
+ });
+ }
+
+ public static void Umlsl_V(AILEmitterCtx Context)
+ {
+ EmitVectorWidenRnRmTernaryOpZx(Context, () =>
+ {
+ Context.Emit(OpCodes.Mul);
+ Context.Emit(OpCodes.Sub);
+ });
+ }
+
public static void Umull_V(AILEmitterCtx Context)
{
EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
@@ -1450,6 +1478,11 @@ namespace ChocolArm64.Instruction
EmitVectorSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate);
}
+ public static void Usubl_V(AILEmitterCtx Context)
+ {
+ EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
+ }
+
public static void Usubw_V(AILEmitterCtx Context)
{
EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));