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authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2018-04-26 04:20:22 +0200
committergdkchan <gab.dark.100@gmail.com>2018-04-25 23:20:22 -0300
commita5ad1e9a064877c05beacd25b64f0bd2e1e1d1dd (patch)
tree7228c5c0ff1abb291830c83a339fe06eb453fa9a /ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
parenta38a72b0622f89897bdcd01b6d00ea6bc142c34f (diff)
Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)
* Update AOpCodeTable.cs * Update AInstEmitSimdLogical.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs
Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs')
-rw-r--r--ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs37
1 files changed, 37 insertions, 0 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
index 2dce7410..f4dcf864 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
@@ -109,6 +109,43 @@ namespace ChocolArm64.Instruction
EmitScalarSet(Context, Op.Rd, Op.Size);
}
+ public static void Cls_V(AILEmitterCtx Context)
+ {
+ MethodInfo MthdInfo = typeof(ASoftFallback).GetMethod(nameof(ASoftFallback.CountLeadingSigns));
+
+ EmitCountLeadingBits(Context, () => Context.EmitCall(MthdInfo));
+ }
+
+ public static void Clz_V(AILEmitterCtx Context)
+ {
+ MethodInfo MthdInfo = typeof(ASoftFallback).GetMethod(nameof(ASoftFallback.CountLeadingZeros));
+
+ EmitCountLeadingBits(Context, () => Context.EmitCall(MthdInfo));
+ }
+
+ private static void EmitCountLeadingBits(AILEmitterCtx Context, Action Emit)
+ {
+ AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
+
+ int Bytes = Context.CurrOp.GetBitsCount() >> 3;
+
+ for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
+ {
+ EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
+
+ Context.EmitLdc_I4(8 << Op.Size);
+
+ Emit();
+
+ EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
+ }
+
+ if (Op.RegisterSize == ARegisterSize.SIMD64)
+ {
+ EmitVectorZeroUpper(Context, Op.Rd);
+ }
+ }
+
public static void Cnt_V(AILEmitterCtx Context)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;