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| author | gdkchan <gab.dark.100@gmail.com> | 2018-05-11 20:10:27 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-05-11 20:10:27 -0300 |
| commit | f9f111bc85a4735391a8479e9a8d36a30ae7f3a9 (patch) | |
| tree | a1b29a56dc151875a58611382b3a67050b32a95c /ChocolArm64/Instruction/AInstEmitSimdCmp.cs | |
| parent | 8e306b3ac14f93ef4e77210c2a23a219760bb55c (diff) | |
Add intrinsics support (#121)
* Initial intrinsics support
* Update tests to work with the new Vector128 type and intrinsics
* Drop SSE4.1 requirement
* Fix copy-paste mistake
Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdCmp.cs')
| -rw-r--r-- | ChocolArm64/Instruction/AInstEmitSimdCmp.cs | 82 |
1 files changed, 73 insertions, 9 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdCmp.cs b/ChocolArm64/Instruction/AInstEmitSimdCmp.cs index f155d7e8..583ad702 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdCmp.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdCmp.cs @@ -3,6 +3,7 @@ using ChocolArm64.State; using ChocolArm64.Translation; using System; using System.Reflection.Emit; +using System.Runtime.Intrinsics.X86; using static ChocolArm64.Instruction.AInstEmitAluHelper; using static ChocolArm64.Instruction.AInstEmitSimdHelper; @@ -13,17 +14,38 @@ namespace ChocolArm64.Instruction { public static void Cmeq_V(AILEmitterCtx Context) { - EmitVectorCmp(Context, OpCodes.Beq_S); + if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg) + { + EmitSse2Call(Context, nameof(Sse2.CompareEqual)); + } + else + { + EmitVectorCmp(Context, OpCodes.Beq_S); + } } public static void Cmge_V(AILEmitterCtx Context) { - EmitVectorCmp(Context, OpCodes.Bge_S); + if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg) + { + EmitSse2Call(Context, nameof(Sse2.CompareGreaterThanOrEqual)); + } + else + { + EmitVectorCmp(Context, OpCodes.Bge_S); + } } public static void Cmgt_V(AILEmitterCtx Context) { - EmitVectorCmp(Context, OpCodes.Bgt_S); + if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg) + { + EmitSse2Call(Context, nameof(Sse2.CompareGreaterThan)); + } + else + { + EmitVectorCmp(Context, OpCodes.Bgt_S); + } } public static void Cmhi_V(AILEmitterCtx Context) @@ -112,32 +134,74 @@ namespace ChocolArm64.Instruction public static void Fcmeq_S(AILEmitterCtx Context) { - EmitScalarFcmp(Context, OpCodes.Beq_S); + if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg) + { + EmitSse2CallF(Context, nameof(Sse2.CompareEqualScalar)); + } + else + { + EmitScalarFcmp(Context, OpCodes.Beq_S); + } } public static void Fcmeq_V(AILEmitterCtx Context) { - EmitVectorFcmp(Context, OpCodes.Beq_S); + if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg) + { + EmitSse2CallF(Context, nameof(Sse2.CompareEqual)); + } + else + { + EmitVectorFcmp(Context, OpCodes.Beq_S); + } } public static void Fcmge_S(AILEmitterCtx Context) { - EmitScalarFcmp(Context, OpCodes.Bge_S); + if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg) + { + EmitSse2CallF(Context, nameof(Sse2.CompareGreaterThanOrEqualScalar)); + } + else + { + EmitScalarFcmp(Context, OpCodes.Bge_S); + } } public static void Fcmge_V(AILEmitterCtx Context) { - EmitVectorFcmp(Context, OpCodes.Bge_S); + if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg) + { + EmitSse2CallF(Context, nameof(Sse2.CompareGreaterThanOrEqual)); + } + else + { + EmitVectorFcmp(Context, OpCodes.Bge_S); + } } public static void Fcmgt_S(AILEmitterCtx Context) { - EmitScalarFcmp(Context, OpCodes.Bgt_S); + if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg) + { + EmitSse2CallF(Context, nameof(Sse2.CompareGreaterThanScalar)); + } + else + { + EmitScalarFcmp(Context, OpCodes.Bgt_S); + } } public static void Fcmgt_V(AILEmitterCtx Context) { - EmitVectorFcmp(Context, OpCodes.Bgt_S); + if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg) + { + EmitSse2CallF(Context, nameof(Sse2.CompareGreaterThan)); + } + else + { + EmitVectorFcmp(Context, OpCodes.Bgt_S); + } } public static void Fcmle_S(AILEmitterCtx Context) |
