diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2018-03-05 16:18:37 -0300 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-03-05 16:18:37 -0300 |
| commit | 59d1b2ad83385dad49cf930e826ce0693b9cee2c (patch) | |
| tree | 3a5cf63453273d8469a63c673dc3929c0d0948fa /ChocolArm64/Decoder/AOpCodeSimdRegElem.cs | |
| parent | 0e343a748d9dcfe50b885b8c0c5e886bc44080ac (diff) | |
Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
Diffstat (limited to 'ChocolArm64/Decoder/AOpCodeSimdRegElem.cs')
| -rw-r--r-- | ChocolArm64/Decoder/AOpCodeSimdRegElem.cs | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs b/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs index d878b12e..127debd1 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs +++ b/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs @@ -8,15 +8,27 @@ namespace ChocolArm64.Decoder public AOpCodeSimdRegElem(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode) { - if ((Size & 1) != 0) + switch (Size) { - Index = (OpCode >> 11) & 1; - } - else - { - Index = (OpCode >> 21) & 1 | - (OpCode >> 10) & 2; + case 1: + Index = (OpCode >> 21) & 1 | + (OpCode >> 10) & 2 | + (OpCode >> 18) & 4; + + Rm &= 0xf; + + break; + + case 2: + Index = (OpCode >> 21) & 1 | + (OpCode >> 10) & 2; + + break; + + default: Emitter = AInstEmit.Und; return; } + + } } }
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