From 59d1b2ad83385dad49cf930e826ce0693b9cee2c Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Mon, 5 Mar 2018 16:18:37 -0300
Subject: Add MUL (vector by element), fix FCVTN, make svcs use MakeError too

---
 ChocolArm64/Decoder/AOpCodeSimdRegElem.cs | 26 +++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

(limited to 'ChocolArm64/Decoder/AOpCodeSimdRegElem.cs')

diff --git a/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs b/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs
index d878b12e..127debd1 100644
--- a/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs
+++ b/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs
@@ -8,15 +8,27 @@ namespace ChocolArm64.Decoder
 
         public AOpCodeSimdRegElem(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
         {
-            if ((Size & 1) != 0)
+            switch (Size)
             {
-                Index = (OpCode >> 11) & 1;
-            }
-            else
-            {
-                Index = (OpCode >> 21) & 1 |
-                        (OpCode >> 10) & 2;
+                case 1:
+                    Index = (OpCode >> 21) & 1 |
+                            (OpCode >> 10) & 2 |
+                            (OpCode >> 18) & 4;
+
+                    Rm &= 0xf;
+
+                    break;
+
+                case 2:
+                    Index = (OpCode >> 21) & 1 |
+                            (OpCode >> 10) & 2;
+
+                    break;
+
+                default: Emitter = AInstEmit.Und; return;
             }
+
+            
         }
     }
 }
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