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authorgdkchan <gab.dark.100@gmail.com>2018-03-05 16:18:37 -0300
committergdkchan <gab.dark.100@gmail.com>2018-03-05 16:18:37 -0300
commit59d1b2ad83385dad49cf930e826ce0693b9cee2c (patch)
tree3a5cf63453273d8469a63c673dc3929c0d0948fa /ChocolArm64/Decoder
parent0e343a748d9dcfe50b885b8c0c5e886bc44080ac (diff)
Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
Diffstat (limited to 'ChocolArm64/Decoder')
-rw-r--r--ChocolArm64/Decoder/AOpCodeSimdReg.cs6
-rw-r--r--ChocolArm64/Decoder/AOpCodeSimdRegElem.cs26
-rw-r--r--ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs22
3 files changed, 44 insertions, 10 deletions
diff --git a/ChocolArm64/Decoder/AOpCodeSimdReg.cs b/ChocolArm64/Decoder/AOpCodeSimdReg.cs
index 10a4aff8..702ffed1 100644
--- a/ChocolArm64/Decoder/AOpCodeSimdReg.cs
+++ b/ChocolArm64/Decoder/AOpCodeSimdReg.cs
@@ -4,9 +4,9 @@ namespace ChocolArm64.Decoder
{
class AOpCodeSimdReg : AOpCodeSimd
{
- public bool Bit3 { get; private set; }
- public int Ra { get; private set; }
- public int Rm { get; private set; }
+ public bool Bit3 { get; private set; }
+ public int Ra { get; private set; }
+ public int Rm { get; protected set; }
public AOpCodeSimdReg(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
diff --git a/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs b/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs
index d878b12e..127debd1 100644
--- a/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs
+++ b/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs
@@ -8,15 +8,27 @@ namespace ChocolArm64.Decoder
public AOpCodeSimdRegElem(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
- if ((Size & 1) != 0)
+ switch (Size)
{
- Index = (OpCode >> 11) & 1;
- }
- else
- {
- Index = (OpCode >> 21) & 1 |
- (OpCode >> 10) & 2;
+ case 1:
+ Index = (OpCode >> 21) & 1 |
+ (OpCode >> 10) & 2 |
+ (OpCode >> 18) & 4;
+
+ Rm &= 0xf;
+
+ break;
+
+ case 2:
+ Index = (OpCode >> 21) & 1 |
+ (OpCode >> 10) & 2;
+
+ break;
+
+ default: Emitter = AInstEmit.Und; return;
}
+
+
}
}
} \ No newline at end of file
diff --git a/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs b/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs
new file mode 100644
index 00000000..e61d7093
--- /dev/null
+++ b/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs
@@ -0,0 +1,22 @@
+using ChocolArm64.Instruction;
+
+namespace ChocolArm64.Decoder
+{
+ class AOpCodeSimdRegElemF : AOpCodeSimdReg
+ {
+ public int Index { get; private set; }
+
+ public AOpCodeSimdRegElemF(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
+ {
+ if ((Size & 1) != 0)
+ {
+ Index = (OpCode >> 11) & 1;
+ }
+ else
+ {
+ Index = (OpCode >> 21) & 1 |
+ (OpCode >> 10) & 2;
+ }
+ }
+ }
+} \ No newline at end of file