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| author | gdkchan <gab.dark.100@gmail.com> | 2022-01-21 12:47:34 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-01-21 12:47:34 -0300 |
| commit | f0824fde9f511e9f6d1cda1f80549c93a5d6ce69 (patch) | |
| tree | 4e4a4c6a7e9be6bef72b9c45dd59be9aa48ec61d /ARMeilleure/IntermediateRepresentation | |
| parent | 7e967d796cf572377f21af3817a22755c5b01cb1 (diff) | |
Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)
* Add host CPU memory barriers for DMB/DSB and ordered load/store
* PPTC version bump
* Revert to old barrier order
Diffstat (limited to 'ARMeilleure/IntermediateRepresentation')
| -rw-r--r-- | ARMeilleure/IntermediateRepresentation/Instruction.cs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/ARMeilleure/IntermediateRepresentation/Instruction.cs b/ARMeilleure/IntermediateRepresentation/Instruction.cs index b675ed1c..b55fe1da 100644 --- a/ARMeilleure/IntermediateRepresentation/Instruction.cs +++ b/ARMeilleure/IntermediateRepresentation/Instruction.cs @@ -26,6 +26,7 @@ namespace ARMeilleure.IntermediateRepresentation Load16, Load8, LoadArgument, + MemoryBarrier, Multiply, Multiply64HighSI, Multiply64HighUI, |