From f0824fde9f511e9f6d1cda1f80549c93a5d6ce69 Mon Sep 17 00:00:00 2001 From: gdkchan Date: Fri, 21 Jan 2022 12:47:34 -0300 Subject: Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) * Add host CPU memory barriers for DMB/DSB and ordered load/store * PPTC version bump * Revert to old barrier order --- ARMeilleure/IntermediateRepresentation/Instruction.cs | 1 + 1 file changed, 1 insertion(+) (limited to 'ARMeilleure/IntermediateRepresentation') diff --git a/ARMeilleure/IntermediateRepresentation/Instruction.cs b/ARMeilleure/IntermediateRepresentation/Instruction.cs index b675ed1c..b55fe1da 100644 --- a/ARMeilleure/IntermediateRepresentation/Instruction.cs +++ b/ARMeilleure/IntermediateRepresentation/Instruction.cs @@ -26,6 +26,7 @@ namespace ARMeilleure.IntermediateRepresentation Load16, Load8, LoadArgument, + MemoryBarrier, Multiply, Multiply64HighSI, Multiply64HighUI, -- cgit v1.2.3