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authorReinUsesLisp <reinuseslisp@airmail.cc>2019-04-29 23:28:28 -0300
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-05-02 21:46:25 -0300
commit002ecbea190de16294d32449c3d2b61e57490dae (patch)
tree323a1f1641e4a9f46c412286750c65470c1de0db /src/video_core/shader/decode/memory.cpp
parent7632a7d6d2cd1fca58dcc714fccac01ec2753547 (diff)
shader_ir/memory: Emit AL2P IR
Diffstat (limited to 'src/video_core/shader/decode/memory.cpp')
-rw-r--r--src/video_core/shader/decode/memory.cpp17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/memory.cpp b/src/video_core/shader/decode/memory.cpp
index ea1092db1..4aa74965f 100644
--- a/src/video_core/shader/decode/memory.cpp
+++ b/src/video_core/shader/decode/memory.cpp
@@ -12,6 +12,8 @@
#include "video_core/engines/shader_bytecode.h"
#include "video_core/shader/shader_ir.h"
+#pragma optimize("", off)
+
namespace VideoCommon::Shader {
using Tegra::Shader::Attribute;
@@ -239,6 +241,21 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
}
break;
}
+ case OpCode::Id::AL2P: {
+ // Ignore al2p.direction since we don't care about it.
+
+ // Calculate emulation fake physical address.
+ const Node fixed_address{Immediate(static_cast<u32>(instr.al2p.address))};
+ const Node reg{GetRegister(instr.gpr8)};
+ const Node fake_address{Operation(OperationCode::IAdd, NO_PRECISE, reg, fixed_address)};
+
+ // Set the fake address to target register.
+ SetRegister(bb, instr.gpr0, fake_address);
+
+ // Signal the shader IR to declare all possible attributes and varyings
+ use_physical_attributes = true;
+ break;
+ }
default:
UNIMPLEMENTED_MSG("Unhandled memory instruction: {}", opcode->get().GetName());
}