| Age | Commit message (Expand) | Author |
|---|
| 2018-10-30 | Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) | Alex Barney |
| 2018-10-23 | Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. ... | LDj3SNuD |
| 2018-09-26 | Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Sca... | gdkchan |
| 2018-08-14 | Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273) | gdkchan |
| 2018-08-05 | More accurate impl of FMINNM/FMAXNM, add vector variants (#296) | gdkchan |
| 2018-07-03 | Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Impr... | LDj3SNuD |
| 2018-06-28 | Add Sse2 fallback to Vector{Extract|Insert}Single methods on the CPU (#193) | gdkchan |
| 2018-05-11 | Add intrinsics support (#121) | gdkchan |
