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path: root/ChocolArm64/AOpCodeTable.cs
AgeCommit message (Expand)Author
2018-07-19AOpCodeTable: Speed up instruction decoding (#284)Merry
2018-07-18Implement Ssubw_V and Usubw_V instructions. (#287)LDj3SNuD
2018-07-14Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)gdkchan
2018-07-03Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions (#200)gdkchan
2018-07-03Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Impr...LDj3SNuD
2018-06-30Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V...LDj3SNuD
2018-06-28Add support for the FMLA (by element/scalar) instruction (#187)gdkchan
2018-06-25Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32c...LDj3SNuD
2018-06-25Add REV16/32 (vector) instructions and fix REV64gdkchan
2018-06-25Add opcodes SQXTUN_S and SQXTUN_V (#184)Rygnus
2018-06-18Add Cmeq_S, Cmge_S, Cmgt_S, Cmhi_S, Cmhs_S, Cmle_S, Cmlt_S (Reg, Zero) & Cmts...LDj3SNuD
2018-06-18Add the FADDP (scalar) instructiongdkchan
2018-06-12Implement Fabs_V (#146)Lordmau5
2018-05-26Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used...gdkchan
2018-05-18Add scalar variants of FCVTZS/FCVTZU, fix a issue on Ryushadergdkchan
2018-04-29Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). (#110)LDj3SNuD
2018-04-25Update AOpCodeTable.cs (#108)LDj3SNuD
2018-04-25Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_...LDj3SNuD
2018-04-21Fix Addp_S in AOpCodeTable. Add 5 Tests: ADDP (scalar), ADDP (vector), ADDV. ...LDj3SNuD
2018-04-20Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tes...LDj3SNuD
2018-04-19Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89)MS-DOS1999
2018-04-18Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. (#88)LDj3SNuD
2018-04-12Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77)LDj3SNuD
2018-04-08Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vecto...LDj3SNuD
2018-04-06Add FMLS (vector) instructiongdkchan
2018-04-05Add FRSQRTS and FCM* instructionsgdkchan
2018-04-05Implement Frsqrte_S (#72)Merry
2018-04-04Add Faddp (vector) instructiongdkchan
2018-04-04Add PRFM (unscaled) instructiongdkchan
2018-04-04Add FNEG (vector) instructiongdkchan
2018-03-30Enable all ld/st (single structure) instructionsgdkchan
2018-03-30Add BIT instructiongdkchan
2018-03-30Add UABD instructiongdkchan
2018-03-30Add UABDL instructiongdkchan
2018-03-30Add UADDL instructiongdkchan
2018-03-30Add UHADD instructiongdkchan
2018-03-24Add FNMADD instructiongdkchan
2018-03-23Add Cls Instruction. (#67)LDj3SNuD
2018-03-23Add Frint Instructions and Tests (#62)MS-DOS1999
2018-03-16Add BFI instruction, even more audout fixesgdkchan
2018-03-15Add MLA (vector by element), fixes some cases of MUL (vector by element)?gdkchan
2018-03-14Add CRC32 instruction and SLI (vector)gdkchan
2018-03-10Fix EmitScalarUnaryOpF and add SSRA (vector)gdkchan
2018-03-09Add FRINTM (vector) instructiongdkchan
2018-03-09Add SHLL instructiongdkchan
2018-03-06Add SMLAL (vector), fix EXT instructiongdkchan
2018-03-05Add MUL (vector by element), fix FCVTN, make svcs use MakeError toogdkchan
2018-03-05Add FCVTL and FCVTN instruction (no Half support yet), stub SvcClearEventgdkchan
2018-03-02Fix REV64 (vector) instructiongdkchan
2018-03-02Add REV64 (vector) instructiongdkchan