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AgeCommit message (Expand)Author
2022-08-25ARMeilleure: Hardware accelerate SHA256 (#3585)merry
2022-08-25Implement some 32-bit Thumb instructions (#3614)gdkchan
2022-08-18Removed unused usings. (#3593)Nicholas Rodine
2022-08-05Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)gdkchan
2022-07-06Implement CPU FCVT Half <-> Double conversion variants (#3439)gdkchan
2022-05-31Refactor CPU interface to allow the implementation of other CPU emulators (#3...gdkchan
2022-03-19InstEmitMemoryEx: Barrier after write on ordered store (#3193)merry
2022-03-05A32: Fix ALU immediate instructions (#3179)merry
2022-03-04Decoder: Exit on trapping instructions, and resume execution at trapping inst...merry
2022-03-04T32: Implement B, B.cond, BL, BLX (#3155)merry
2022-02-22T32: Implement ALU (shifted register) instructions (#3135)merry
2022-02-22A32: Fix BLX and BXWritePC (#3151)merry
2022-02-18Enable CPU JIT cache invalidation (#2965)gdkchan
2022-02-18Decoders: Add IOpCode32HasSetFlags (#3136)merry
2022-02-17ARMeilleure: Thumb support (All T16 instructions) (#3105)merry
2022-02-17Use ReadOnlySpan<byte> compiler optimization for static data (#3130)Berkan Diler
2022-02-11InstEmitMemory32: Literal loads always have word-aligned PC (#3104)merry
2022-02-08ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)merry
2022-02-06ARMeilleure: A32: Implement SHADD8 (#3086)merry
2022-01-29Fix small precision error on CPU reciprocal estimate instructions (#3061)gdkchan
2022-01-21Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)gdkchan
2022-01-19Implement FCVTNS (Scalar GP) (#2953)sharmander
2022-01-16Fix return type mismatch on 32-bit titles (#3000)gdkchan
2022-01-04CPU - Implement FCVTMS (Vector) (#2937)sharmander
2021-12-19Implement CSDB instruction (#2927)gdkchan
2021-12-08Implement UHADD8 instruction (#2908)Piyachet Kanda
2021-09-29Use normal memory store path for DC ZVA (#2693)riperiperi
2021-09-14Refactor `PtcInfo` (#2625)FICTURE7
2021-08-27Implement MSR instruction for A32 (#2585)Mary
2021-08-17Reduce JIT GC allocations (#2515)FICTURE7
2021-06-23Implement VORN (register) Arm32 instruction (#2396)gdkchan
2021-05-29Add multi-level function table (#2228)FICTURE7
2021-05-24POWER - Performance Optimizations With Extensive Ramifications (#2286)riperiperi
2021-05-24Improve accuracy of reciprocal step instructions (#2305)gdkchan
2021-05-20Use branch instead of tailcall for recursive calls (#2282)FICTURE7
2021-05-20Add `BIC/ORR Vd.T, #imm` fast path (#2279)FICTURE7
2021-05-13Fold constant offsets and group constant addresses (#2285)gdkchan
2021-04-18Add inlined on translation call counting (#2190)FICTURE7
2021-04-02Improve `StoreToContext` emission (#2155)FICTURE7
2021-03-25Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)LDj3SNuD
2021-02-22Implement VCNT instruction (#1963)mageven
2021-02-17Fix memory tracking performance regression (#2026)gdkchan
2021-02-16Validate CPU virtual addresses on access (#1987)gdkchan
2021-01-28Lower precision of estimate instruction results to match Arm behavior (#1943)gdkchan
2021-01-26Implement PRFM (register variant) as NOP (#1956)mageven
2021-01-25Add VCLZ.* fast path (#1917)FICTURE7
2021-01-20CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests...LDj3SNuD
2021-01-04CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian...LDj3SNuD
2020-12-17Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow...LDj3SNuD
2020-12-17PPTC Follow-up. (#1712)LDj3SNuD
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