| Age | Commit message (Expand) | Author |
|---|
| 2020-07-13 | Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335) | LDj3SNuD |
| 2020-07-13 | Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli vari... | riperiperi |
| 2020-06-24 | Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303) | riperiperi |
| 2020-06-14 | VABS takes one input register, not two. (#1300) | riperiperi |
| 2020-05-27 | Add FMaxNmV & FMinNmV Inst.s with Test. (#1279) | LDj3SNuD |
| 2020-03-24 | Add Fcvtas_S/V & Fcvtau_S/V. (#1018) | LDj3SNuD |
| 2020-03-20 | Move the MakeOp to OpCodeTable class, for reduce the use of ConcurrentDiction... | Chenj168 |
| 2020-03-14 | Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982) | riperiperi |
| 2020-03-11 | Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other... | gdkchan |
| 2020-03-10 | Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960) | gdkchan |
| 2020-03-07 | A64 SIMD LDP and STP with size = 0b11 is undefined (#971) | gdkchan |
| 2020-03-01 | Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954) | gdkchan |
| 2020-03-01 | Implement FACGE and FACGT (Scalar and Vector) AArch64 SIMD instructions (#956) | gdkchan |
| 2020-02-24 | Add most of the A32 instruction set to ARMeilleure (#897) | riperiperi |
| 2019-10-24 | Add Sli_S/V & Sri_S/V inst.s (fast & slow paths), with Tests. (#797) | LDj3SNuD |
| 2019-10-04 | Add Tbx Inst. (fast & slow paths), with Tests. (#782) | LDj3SNuD |
| 2019-08-08 | Add a new JIT compiler for CPU code (#693) | gdkchan |
