aboutsummaryrefslogtreecommitdiff
path: root/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs
diff options
context:
space:
mode:
Diffstat (limited to 'src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs')
-rw-r--r--src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs
index 36564064..3391a2c1 100644
--- a/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs
+++ b/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs
@@ -1131,5 +1131,37 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
return false;
}
+
+ public static bool IsPartialRegisterUpdateMemory(this InstName name)
+ {
+ switch (name)
+ {
+ case InstName.Ld1AdvsimdSnglAsNoPostIndex:
+ case InstName.Ld1AdvsimdSnglAsPostIndex:
+ case InstName.Ld2AdvsimdSnglAsNoPostIndex:
+ case InstName.Ld2AdvsimdSnglAsPostIndex:
+ case InstName.Ld3AdvsimdSnglAsNoPostIndex:
+ case InstName.Ld3AdvsimdSnglAsPostIndex:
+ case InstName.Ld4AdvsimdSnglAsNoPostIndex:
+ case InstName.Ld4AdvsimdSnglAsPostIndex:
+ return true;
+ }
+
+ return false;
+ }
+
+ public static bool IsPrefetchMemory(this InstName name)
+ {
+ switch (name)
+ {
+ case InstName.PrfmImm:
+ case InstName.PrfmLit:
+ case InstName.PrfmReg:
+ case InstName.Prfum:
+ return true;
+ }
+
+ return false;
+ }
}
}