diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2024-03-26 23:33:24 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-26 23:33:24 -0300 |
| commit | b323a017385ac6e08db4025fe4ef1bfbb41607ab (patch) | |
| tree | 33392d69cea70232cb0342e38a924dc31fb22719 /src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs | |
| parent | f6d24449b6e1ebe753c0a8095a435820c0948f19 (diff) | |
Implement host tracked memory manager mode (#6356)
* Add host tracked memory manager mode
* Skipping flush is no longer needed
* Formatting + revert unrelated change
* LightningJit: Ensure that dest register is saved for load ops that do partial updates
* avoid allocations when doing address space lookup
Add missing improvement
* IsRmwMemory -> IsPartialRegisterUpdateMemory
* Ensure we iterate all private allocations in range
* PR feedback and potential fixes
* Simplified bridges a lot
* Skip calling SignalMappingChanged if Guest is true
* Late map bridge too
* Force address masking for prefetch instructions
* Reprotection for bridges
* Move partition list validation to separate debug method
* Move host tracked related classes to HostTracked folder
* New HostTracked namespace
* Move host tracked modes to the end of enum to avoid PPTC invalidation
---------
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Diffstat (limited to 'src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs')
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs index 36564064..3391a2c1 100644 --- a/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs @@ -1131,5 +1131,37 @@ namespace Ryujinx.Cpu.LightningJit.Arm64 return false; } + + public static bool IsPartialRegisterUpdateMemory(this InstName name) + { + switch (name) + { + case InstName.Ld1AdvsimdSnglAsNoPostIndex: + case InstName.Ld1AdvsimdSnglAsPostIndex: + case InstName.Ld2AdvsimdSnglAsNoPostIndex: + case InstName.Ld2AdvsimdSnglAsPostIndex: + case InstName.Ld3AdvsimdSnglAsNoPostIndex: + case InstName.Ld3AdvsimdSnglAsPostIndex: + case InstName.Ld4AdvsimdSnglAsNoPostIndex: + case InstName.Ld4AdvsimdSnglAsPostIndex: + return true; + } + + return false; + } + + public static bool IsPrefetchMemory(this InstName name) + { + switch (name) + { + case InstName.PrfmImm: + case InstName.PrfmLit: + case InstName.PrfmReg: + case InstName.Prfum: + return true; + } + + return false; + } } } |
