Fix Frecpe_S/V and Frsqrte_S/V (full FP emu.). Add Sse Opt. & SoftFloat Impl. for Fcmeq/ge/gt/le/lt_S/V (Reg & Zero), Faddp_S/V, Fmaxp_V, Fminp_V Inst.; add Sse Opt. for Shll_V, S/Ushll_V Inst.; improve Sse Opt. for Xtn_V Inst.. Add Tests. (#543)

* Update Optimizations.cs

* Update InstEmitSimdShift.cs

* Update InstEmitSimdHelper.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdMove.cs

* Update SoftFloat.cs

* Update InstEmitSimdCmp.cs

* Update CpuTestSimdShImm.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Nit.

* Update SoftFloat.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdHelper.cs

* Update CpuTestSimd.cs

* Explicit some implicit casts.

* Simplify some powers; nits.

* Update OpCodeTable.cs

* Update InstEmitSimdArithmetic.cs

* Update CpuTestSimdReg.cs

* Update InstEmitSimdArithmetic.cs

3 files changed, 614 insertions, 59 deletions

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
index 54889eee..565b6613 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
@@ -256,6 +256,112 @@ namespace Ryujinx.Tests.Cpu
 #endregion
 
 #region "ValueSource (Opcodes)"
+        private static uint[] _F_Abs_Neg_Recpx_Sqrt_S_S_()
+        {
+            return new uint[]
+            {
+                0x1E20C020u, // FABS   S0, S1
+                0x1E214020u, // FNEG   S0, S1
+                0x5EA1F820u, // FRECPX S0, S1
+                0x1E21C020u  // FSQRT  S0, S1
+            };
+        }
+
+        private static uint[] _F_Abs_Neg_Recpx_Sqrt_S_D_()
+        {
+            return new uint[]
+            {
+                0x1E60C020u, // FABS   D0, D1
+                0x1E614020u, // FNEG   D0, D1
+                0x5EE1F820u, // FRECPX D0, D1
+                0x1E61C020u  // FSQRT  D0, D1
+            };
+        }
+
+        private static uint[] _F_Abs_Neg_Sqrt_V_2S_4S_()
+        {
+            return new uint[]
+            {
+                0x0EA0F800u, // FABS  V0.2S, V0.2S
+                0x2EA0F800u, // FNEG  V0.2S, V0.2S
+                0x2EA1F800u  // FSQRT V0.2S, V0.2S
+            };
+        }
+
+        private static uint[] _F_Abs_Neg_Sqrt_V_2D_()
+        {
+            return new uint[]
+            {
+                0x4EE0F800u, // FABS  V0.2D, V0.2D
+                0x6EE0F800u, // FNEG  V0.2D, V0.2D
+                0x6EE1F800u  // FSQRT V0.2D, V0.2D
+            };
+        }
+
+        private static uint[] _F_Add_P_S_2SS_()
+        {
+            return new uint[]
+            {
+                0x7E30D820u // FADDP S0, V1.2S
+            };
+        }
+
+        private static uint[] _F_Add_P_S_2DD_()
+        {
+            return new uint[]
+            {
+                0x7E70D820u // FADDP D0, V1.2D
+            };
+        }
+
+        private static uint[] _F_Cm_EqGeGtLeLt_S_S_()
+        {
+            return new uint[]
+            {
+                0x5EA0D820u, // FCMEQ S0, S1, #0.0
+                0x7EA0C820u, // FCMGE S0, S1, #0.0
+                0x5EA0C820u, // FCMGT S0, S1, #0.0
+                0x7EA0D820u, // FCMLE S0, S1, #0.0
+                0x5EA0E820u  // FCMLT S0, S1, #0.0
+            };
+        }
+
+        private static uint[] _F_Cm_EqGeGtLeLt_S_D_()
+        {
+            return new uint[]
+            {
+                0x5EE0D820u, // FCMEQ D0, D1, #0.0
+                0x7EE0C820u, // FCMGE D0, D1, #0.0
+                0x5EE0C820u, // FCMGT D0, D1, #0.0
+                0x7EE0D820u, // FCMLE D0, D1, #0.0
+                0x5EE0E820u  // FCMLT D0, D1, #0.0
+            };
+        }
+
+        private static uint[] _F_Cm_EqGeGtLeLt_V_2S_4S_()
+        {
+            return new uint[]
+            {
+                0x0EA0D800u, // FCMEQ V0.2S, V0.2S, #0.0
+                0x2EA0C800u, // FCMGE V0.2S, V0.2S, #0.0
+                0x0EA0C800u, // FCMGT V0.2S, V0.2S, #0.0
+                0x2EA0D800u, // FCMLE V0.2S, V0.2S, #0.0
+                0x0EA0E800u  // FCMLT V0.2S, V0.2S, #0.0
+            };
+        }
+
+        private static uint[] _F_Cm_EqGeGtLeLt_V_2D_()
+        {
+            return new uint[]
+            {
+                0x4EE0D800u, // FCMEQ V0.2D, V0.2D, #0.0
+                0x6EE0C800u, // FCMGE V0.2D, V0.2D, #0.0
+                0x4EE0C800u, // FCMGT V0.2D, V0.2D, #0.0
+                0x6EE0D800u, // FCMLE V0.2D, V0.2D, #0.0
+                0x4EE0E800u  // FCMLT V0.2D, V0.2D, #0.0
+            };
+        }
+
         private static uint[] _F_Cmp_Cmpe_S_S_()
         {
             return new uint[]
@@ -366,45 +472,39 @@ namespace Ryujinx.Tests.Cpu
             };
         }
 
-        private static uint[] _F_Abs_Neg_Recpx_Sqrt_S_S_()
+        private static uint[] _F_Recpe_Rsqrte_S_S_()
         {
             return new uint[]
             {
-                0x1E20C020u, // FABS   S0, S1
-                0x1E214020u, // FNEG   S0, S1
-                0x5EA1F820u, // FRECPX S0, S1
-                0x1E21C020u  // FSQRT  S0, S1
+                0x5EA1D820u, // FRECPE  S0, S1
+                0x7EA1D820u  // FRSQRTE S0, S1
             };
         }
 
-        private static uint[] _F_Abs_Neg_Recpx_Sqrt_S_D_()
+        private static uint[] _F_Recpe_Rsqrte_S_D_()
         {
             return new uint[]
             {
-                0x1E60C020u, // FABS   D0, D1
-                0x1E614020u, // FNEG   D0, D1
-                0x5EE1F820u, // FRECPX D0, D1
-                0x1E61C020u  // FSQRT  D0, D1
+                0x5EE1D820u, // FRECPE  D0, D1
+                0x7EE1D820u  // FRSQRTE D0, D1
             };
         }
 
-        private static uint[] _F_Abs_Neg_Sqrt_V_2S_4S_()
+        private static uint[] _F_Recpe_Rsqrte_V_2S_4S_()
         {
             return new uint[]
             {
-                0x0EA0F800u, // FABS  V0.2S, V0.2S
-                0x2EA0F800u, // FNEG  V0.2S, V0.2S
-                0x2EA1F800u  // FSQRT V0.2S, V0.2S
+                0x0EA1D800u, // FRECPE  V0.2S, V0.2S
+                0x2EA1D800u  // FRSQRTE V0.2S, V0.2S
             };
         }
 
-        private static uint[] _F_Abs_Neg_Sqrt_V_2D_()
+        private static uint[] _F_Recpe_Rsqrte_V_2D_()
         {
             return new uint[]
             {
-                0x4EE0F800u, // FABS  V0.2D, V0.2D
-                0x6EE0F800u, // FNEG  V0.2D, V0.2D
-                0x6EE1F800u  // FSQRT V0.2D, V0.2D
+                0x4EE1D800u, // FRECPE  V0.2D, V0.2D
+                0x6EE1D800u  // FRSQRTE V0.2D, V0.2D
             };
         }
 
@@ -964,6 +1064,202 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Pairwise] [Explicit]
+        public void F_Abs_Neg_Recpx_Sqrt_S_S([ValueSource("_F_Abs_Neg_Recpx_Sqrt_S_S_")] uint opcodes,
+                                             [ValueSource("_1S_F_")] ulong a)
+        {
+            ulong z = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0(a);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+            fpcr |= rnd & (1 << (int)Fpcr.Dn);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Abs_Neg_Recpx_Sqrt_S_D([ValueSource("_F_Abs_Neg_Recpx_Sqrt_S_D_")] uint opcodes,
+                                             [ValueSource("_1D_F_")] ulong a)
+        {
+            ulong z = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> v0 = MakeVectorE1(z);
+            Vector128<float> v1 = MakeVectorE0(a);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+            fpcr |= rnd & (1 << (int)Fpcr.Dn);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Abs_Neg_Sqrt_V_2S_4S([ValueSource("_F_Abs_Neg_Sqrt_V_2S_4S_")] uint opcodes,
+                                           [Values(0u)]     uint rd,
+                                           [Values(1u, 0u)] uint rn,
+                                           [ValueSource("_2S_F_")] ulong z,
+                                           [ValueSource("_2S_F_")] ulong a,
+                                           [Values(0b0u, 0b1u)] uint q) // <2S, 4S>
+        {
+            opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcodes |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(a, a * q);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+            fpcr |= rnd & (1 << (int)Fpcr.Dn);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Abs_Neg_Sqrt_V_2D([ValueSource("_F_Abs_Neg_Sqrt_V_2D_")] uint opcodes,
+                                        [Values(0u)]     uint rd,
+                                        [Values(1u, 0u)] uint rn,
+                                        [ValueSource("_1D_F_")] ulong z,
+                                        [ValueSource("_1D_F_")] ulong a)
+        {
+            opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(a, a);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+            fpcr |= rnd & (1 << (int)Fpcr.Dn);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Add_P_S_2SS([ValueSource("_F_Add_P_S_2SS_")] uint opcodes,
+                                  [ValueSource("_2S_F_")] ulong a)
+        {
+            ulong z = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0(a);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+            fpcr |= rnd & (1 << (int)Fpcr.Dn);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Add_P_S_2DD([ValueSource("_F_Add_P_S_2DD_")] uint opcodes,
+                                  [ValueSource("_1D_F_")] ulong a)
+        {
+            ulong z = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> v0 = MakeVectorE1(z);
+            Vector128<float> v1 = MakeVectorE0E1(a, a);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+            fpcr |= rnd & (1 << (int)Fpcr.Dn);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Cm_EqGeGtLeLt_S_S([ValueSource("_F_Cm_EqGeGtLeLt_S_S_")] uint opcodes,
+                                        [ValueSource("_1S_F_")] ulong a)
+        {
+            ulong z = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0(a);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Cm_EqGeGtLeLt_S_D([ValueSource("_F_Cm_EqGeGtLeLt_S_D_")] uint opcodes,
+                                        [ValueSource("_1D_F_")] ulong a)
+        {
+            ulong z = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> v0 = MakeVectorE1(z);
+            Vector128<float> v1 = MakeVectorE0(a);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Cm_EqGeGtLeLt_V_2S_4S([ValueSource("_F_Cm_EqGeGtLeLt_V_2S_4S_")] uint opcodes,
+                                            [Values(0u)]     uint rd,
+                                            [Values(1u, 0u)] uint rn,
+                                            [ValueSource("_2S_F_")] ulong z,
+                                            [ValueSource("_2S_F_")] ulong a,
+                                            [Values(0b0u, 0b1u)] uint q) // <2S, 4S>
+        {
+            opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcodes |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(a, a * q);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Cm_EqGeGtLeLt_V_2D([ValueSource("_F_Cm_EqGeGtLeLt_V_2D_")] uint opcodes,
+                                         [Values(0u)]     uint rd,
+                                         [Values(1u, 0u)] uint rn,
+                                         [ValueSource("_1D_F_")] ulong z,
+                                         [ValueSource("_1D_F_")] ulong a)
+        {
+            opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(a, a);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
         public void F_Cmp_Cmpe_S_S([ValueSource("_F_Cmp_Cmpe_S_S_")] uint opcodes,
                                    [ValueSource("_1S_F_")] ulong a)
         {
@@ -1089,13 +1385,13 @@ namespace Ryujinx.Tests.Cpu
                                        [Values(1u, 0u)] uint rn,
                                        [ValueSource("_4H_F_")] ulong z,
                                        [ValueSource("_4H_F_")] ulong a,
-                                       [Values(0b0u, 0b1u)] uint q, // <4H, 8H>
+                                       [Values(0b0u, 0b1u)] uint q, // <4H4S, 8H4S>
                                        [Values(RMode.Rn)] RMode rMode)
         {
             opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
             opcodes |= ((q & 1) << 30);
 
-            Vector128<float> v0 = MakeVectorE0E1(q == 0u ? z : 0ul, q == 1u ? z : 0ul);
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
             Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
 
             int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
@@ -1116,12 +1412,12 @@ namespace Ryujinx.Tests.Cpu
                                        [Values(1u, 0u)] uint rn,
                                        [ValueSource("_2S_F_")] ulong z,
                                        [ValueSource("_2S_F_")] ulong a,
-                                       [Values(0b0u, 0b1u)] uint q) // <2S, 4S>
+                                       [Values(0b0u, 0b1u)] uint q) // <2S2D, 4S2D>
         {
             opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
             opcodes |= ((q & 1) << 30);
 
-            Vector128<float> v0 = MakeVectorE0E1(q == 0u ? z : 0ul, q == 1u ? z : 0ul);
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
             Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
 
             SingleOpcode(opcodes, v0: v0, v1: v1);
@@ -1135,7 +1431,7 @@ namespace Ryujinx.Tests.Cpu
                                        [Values(1u, 0u)] uint rn,
                                        [ValueSource("_2S_F_")] ulong z,
                                        [ValueSource("_2S_F_")] ulong a,
-                                       [Values(0b0u, 0b1u)] uint q, // <4H, 8H>
+                                       [Values(0b0u, 0b1u)] uint q, // <4S4H, 4S8H>
                                        [Values(RMode.Rn)] RMode rMode)
         {
             opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -1162,7 +1458,7 @@ namespace Ryujinx.Tests.Cpu
                                        [Values(1u, 0u)] uint rn,
                                        [ValueSource("_1D_F_")] ulong z,
                                        [ValueSource("_1D_F_")] ulong a,
-                                       [Values(0b0u, 0b1u)] uint q) // <2S, 4S>
+                                       [Values(0b0u, 0b1u)] uint q) // <2D2S, 2D4S>
         {
             opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
             opcodes |= ((q & 1) << 30);
@@ -1176,48 +1472,53 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Pairwise] [Explicit]
-        public void F_Abs_Neg_Recpx_Sqrt_S_S([ValueSource("_F_Abs_Neg_Recpx_Sqrt_S_S_")] uint opcodes,
-                                             [ValueSource("_1S_F_")] ulong a)
+        public void F_Recpe_Rsqrte_S_S([ValueSource("_F_Recpe_Rsqrte_S_S_")] uint opcodes,
+                                       [ValueSource("_1S_F_")] ulong a,
+                                       [Values(RMode.Rn)] RMode rMode)
         {
             ulong z = TestContext.CurrentContext.Random.NextULong();
             Vector128<float> v0 = MakeVectorE0E1(z, z);
-            Vector128<float> v1 = MakeVectorE0E1(a, z);
+            Vector128<float> v1 = MakeVectorE0(a);
 
             int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
 
-            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+            int fpcr = (int)rMode << (int)Fpcr.RMode;
+            fpcr |= rnd & (1 << (int)Fpcr.Fz);
             fpcr |= rnd & (1 << (int)Fpcr.Dn);
 
             SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
 
-            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Ofc | Fpsr.Ufc | Fpsr.Ixc | Fpsr.Idc);
         }
 
         [Test, Pairwise] [Explicit]
-        public void F_Abs_Neg_Recpx_Sqrt_S_D([ValueSource("_F_Abs_Neg_Recpx_Sqrt_S_D_")] uint opcodes,
-                                             [ValueSource("_1D_F_")] ulong a)
+        public void F_Recpe_Rsqrte_S_D([ValueSource("_F_Recpe_Rsqrte_S_D_")] uint opcodes,
+                                       [ValueSource("_1D_F_")] ulong a,
+                                       [Values(RMode.Rn)] RMode rMode)
         {
             ulong z = TestContext.CurrentContext.Random.NextULong();
             Vector128<float> v0 = MakeVectorE1(z);
-            Vector128<float> v1 = MakeVectorE0E1(a, z);
+            Vector128<float> v1 = MakeVectorE0(a);
 
             int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
 
-            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+            int fpcr = (int)rMode << (int)Fpcr.RMode;
+            fpcr |= rnd & (1 << (int)Fpcr.Fz);
             fpcr |= rnd & (1 << (int)Fpcr.Dn);
 
             SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
 
-            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Ofc | Fpsr.Ufc | Fpsr.Ixc | Fpsr.Idc);
         }
 
         [Test, Pairwise] [Explicit]
-        public void F_Abs_Neg_Sqrt_V_2S_4S([ValueSource("_F_Abs_Neg_Sqrt_V_2S_4S_")] uint opcodes,
+        public void F_Recpe_Rsqrte_V_2S_4S([ValueSource("_F_Recpe_Rsqrte_V_2S_4S_")] uint opcodes,
                                            [Values(0u)]     uint rd,
                                            [Values(1u, 0u)] uint rn,
                                            [ValueSource("_2S_F_")] ulong z,
                                            [ValueSource("_2S_F_")] ulong a,
-                                           [Values(0b0u, 0b1u)] uint q) // <2S, 4S>
+                                           [Values(0b0u, 0b1u)] uint q, // <2S, 4S>
+                                           [Values(RMode.Rn)] RMode rMode)
         {
             opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
             opcodes |= ((q & 1) << 30);
@@ -1227,20 +1528,22 @@ namespace Ryujinx.Tests.Cpu
 
             int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
 
-            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+            int fpcr = (int)rMode << (int)Fpcr.RMode;
+            fpcr |= rnd & (1 << (int)Fpcr.Fz);
             fpcr |= rnd & (1 << (int)Fpcr.Dn);
 
             SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
 
-            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Ofc | Fpsr.Ufc | Fpsr.Ixc | Fpsr.Idc);
         }
 
         [Test, Pairwise] [Explicit]
-        public void F_Abs_Neg_Sqrt_V_2D([ValueSource("_F_Abs_Neg_Sqrt_V_2D_")] uint opcodes,
+        public void F_Recpe_Rsqrte_V_2D([ValueSource("_F_Recpe_Rsqrte_V_2D_")] uint opcodes,
                                         [Values(0u)]     uint rd,
                                         [Values(1u, 0u)] uint rn,
                                         [ValueSource("_1D_F_")] ulong z,
-                                        [ValueSource("_1D_F_")] ulong a)
+                                        [ValueSource("_1D_F_")] ulong a,
+                                        [Values(RMode.Rn)] RMode rMode)
         {
             opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
 
@@ -1249,12 +1552,13 @@ namespace Ryujinx.Tests.Cpu
 
             int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
 
-            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+            int fpcr = (int)rMode << (int)Fpcr.RMode;
+            fpcr |= rnd & (1 << (int)Fpcr.Fz);
             fpcr |= rnd & (1 << (int)Fpcr.Dn);
 
             SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
 
-            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Ofc | Fpsr.Ufc | Fpsr.Ixc | Fpsr.Idc);
         }
 
         [Test, Pairwise, Description("NEG <V><d>, <V><n>")]
@@ -1662,6 +1966,27 @@ namespace Ryujinx.Tests.Cpu
             CompareAgainstUnicorn();
         }
 
+        [Test, Pairwise, Description("SHLL{2} <Vd>.<Ta>, <Vn>.<Tb>, #<shift>")]
+        public void Shll_V([Values(0u)]     uint rd,
+                           [Values(1u, 0u)] uint rn,
+                           [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
+                           [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong a,
+                           [Values(0b00u, 0b01u, 0b10u)] uint size, // <shift: 8, 16, 32>
+                           [Values(0b0u, 0b1u)] uint q)
+        {
+            uint opcode = 0x2E213800; // SHLL V0.8H, V0.8B, #8
+            opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcode |= ((size & 3) << 22);
+            opcode |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
+
+            SingleOpcode(opcode, v0: v0, v1: v1);
+
+            CompareAgainstUnicorn();
+        }
+
         [Test, Pairwise, Description("SQABS <V><d>, <V><n>")]
         public void Sqabs_S_B_H_S_D([Values(0u)]     uint rd,
                                     [Values(1u, 0u)] uint rn,
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
index cceb8b10..8d2f4e9a 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
@@ -206,6 +206,7 @@ namespace Ryujinx.Tests.Cpu
         {
             return new uint[]
             {
+                0x7EA2D420u, // FABD  S0, S1, S2
                 0x1E222820u, // FADD  S0, S1, S2
                 0x1E221820u, // FDIV  S0, S1, S2
                 0x1E220820u, // FMUL  S0, S1, S2
@@ -218,6 +219,7 @@ namespace Ryujinx.Tests.Cpu
         {
             return new uint[]
             {
+                0x7EE2D420u, // FABD  D0, D1, D2
                 0x1E622820u, // FADD  D0, D1, D2
                 0x1E621820u, // FDIV  D0, D1, D2
                 0x1E620820u, // FMUL  D0, D1, D2
@@ -226,11 +228,13 @@ namespace Ryujinx.Tests.Cpu
             };
         }
 
-        private static uint[] _F_Add_Div_Mul_Mulx_Sub_V_2S_4S_()
+        private static uint[] _F_Add_Div_Mul_Mulx_Sub_P_V_2S_4S_()
         {
             return new uint[]
             {
+                0x2EA0D400u, // FABD  V0.2S, V0.2S, V0.2S
                 0x0E20D400u, // FADD  V0.2S, V0.2S, V0.2S
+                0x2E20D400u, // FADDP V0.2S, V0.2S, V0.2S
                 0x2E20FC00u, // FDIV  V0.2S, V0.2S, V0.2S
                 0x2E20DC00u, // FMUL  V0.2S, V0.2S, V0.2S
                 0x0E20DC00u, // FMULX V0.2S, V0.2S, V0.2S
@@ -238,11 +242,13 @@ namespace Ryujinx.Tests.Cpu
             };
         }
 
-        private static uint[] _F_Add_Div_Mul_Mulx_Sub_V_2D_()
+        private static uint[] _F_Add_Div_Mul_Mulx_Sub_P_V_2D_()
         {
             return new uint[]
             {
+                0x6EE0D400u, // FABD  V0.2D, V0.2D, V0.2D
                 0x4E60D400u, // FADD  V0.2D, V0.2D, V0.2D
+                0x6E60D400u, // FADDP V0.2D, V0.2D, V0.2D
                 0x6E60FC00u, // FDIV  V0.2D, V0.2D, V0.2D
                 0x6E60DC00u, // FMUL  V0.2D, V0.2D, V0.2D
                 0x4E60DC00u, // FMULX V0.2D, V0.2D, V0.2D
@@ -250,6 +256,46 @@ namespace Ryujinx.Tests.Cpu
             };
         }
 
+        private static uint[] _F_Cm_EqGeGt_S_S_()
+        {
+            return new uint[]
+            {
+                0x5E22E420u, // FCMEQ S0, S1, S2
+                0x7E22E420u, // FCMGE S0, S1, S2
+                0x7EA2E420u  // FCMGT S0, S1, S2
+            };
+        }
+
+        private static uint[] _F_Cm_EqGeGt_S_D_()
+        {
+            return new uint[]
+            {
+                0x5E62E420u, // FCMEQ D0, D1, D2
+                0x7E62E420u, // FCMGE D0, D1, D2
+                0x7EE2E420u  // FCMGT D0, D1, D2
+            };
+        }
+
+        private static uint[] _F_Cm_EqGeGt_V_2S_4S_()
+        {
+            return new uint[]
+            {
+                0x0E20E400u, // FCMEQ V0.2S, V0.2S, V0.2S
+                0x2E20E400u, // FCMGE V0.2S, V0.2S, V0.2S
+                0x2EA0E400u  // FCMGT V0.2S, V0.2S, V0.2S
+            };
+        }
+
+        private static uint[] _F_Cm_EqGeGt_V_2D_()
+        {
+            return new uint[]
+            {
+                0x4E60E400u, // FCMEQ V0.2D, V0.2D, V0.2D
+                0x6E60E400u, // FCMGE V0.2D, V0.2D, V0.2D
+                0x6EE0E400u  // FCMGT V0.2D, V0.2D, V0.2D
+            };
+        }
+
         private static uint[] _F_Cmp_Cmpe_S_S_()
         {
             return new uint[]
@@ -1285,14 +1331,14 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Pairwise] [Explicit]
-        public void F_Add_Div_Mul_Mulx_Sub_V_2S_4S([ValueSource("_F_Add_Div_Mul_Mulx_Sub_V_2S_4S_")] uint opcodes,
-                                                   [Values(0u)]     uint rd,
-                                                   [Values(1u, 0u)] uint rn,
-                                                   [Values(2u, 0u)] uint rm,
-                                                   [ValueSource("_2S_F_")] ulong z,
-                                                   [ValueSource("_2S_F_")] ulong a,
-                                                   [ValueSource("_2S_F_")] ulong b,
-                                                   [Values(0b0u, 0b1u)] uint q) // <2S, 4S>
+        public void F_Add_Div_Mul_Mulx_Sub_P_V_2S_4S([ValueSource("_F_Add_Div_Mul_Mulx_Sub_P_V_2S_4S_")] uint opcodes,
+                                                     [Values(0u)]     uint rd,
+                                                     [Values(1u, 0u)] uint rn,
+                                                     [Values(2u, 0u)] uint rm,
+                                                     [ValueSource("_2S_F_")] ulong z,
+                                                     [ValueSource("_2S_F_")] ulong a,
+                                                     [ValueSource("_2S_F_")] ulong b,
+                                                     [Values(0b0u, 0b1u)] uint q) // <2S, 4S>
         {
             opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
             opcodes |= ((q & 1) << 30);
@@ -1312,13 +1358,13 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Pairwise] [Explicit]
-        public void F_Add_Div_Mul_Mulx_Sub_V_2D([ValueSource("_F_Add_Div_Mul_Mulx_Sub_V_2D_")] uint opcodes,
-                                                [Values(0u)]     uint rd,
-                                                [Values(1u, 0u)] uint rn,
-                                                [Values(2u, 0u)] uint rm,
-                                                [ValueSource("_1D_F_")] ulong z,
-                                                [ValueSource("_1D_F_")] ulong a,
-                                                [ValueSource("_1D_F_")] ulong b)
+        public void F_Add_Div_Mul_Mulx_Sub_P_V_2D([ValueSource("_F_Add_Div_Mul_Mulx_Sub_P_V_2D_")] uint opcodes,
+                                                  [Values(0u)]     uint rd,
+                                                  [Values(1u, 0u)] uint rn,
+                                                  [Values(2u, 0u)] uint rm,
+                                                  [ValueSource("_1D_F_")] ulong z,
+                                                  [ValueSource("_1D_F_")] ulong a,
+                                                  [ValueSource("_1D_F_")] ulong b)
         {
             opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
 
@@ -1337,6 +1383,94 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Pairwise] [Explicit]
+        public void F_Cm_EqGeGt_S_S([ValueSource("_F_Cm_EqGeGt_S_S_")] uint opcodes,
+                                    [ValueSource("_1S_F_")] ulong a,
+                                    [ValueSource("_1S_F_")] ulong b)
+        {
+            ulong z = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0(a);
+            Vector128<float> v2 = MakeVectorE0(b);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Cm_EqGeGt_S_D([ValueSource("_F_Cm_EqGeGt_S_D_")] uint opcodes,
+                                    [ValueSource("_1D_F_")] ulong a,
+                                    [ValueSource("_1D_F_")] ulong b)
+        {
+            ulong z = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> v0 = MakeVectorE1(z);
+            Vector128<float> v1 = MakeVectorE0(a);
+            Vector128<float> v2 = MakeVectorE0(b);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Cm_EqGeGt_V_2S_4S([ValueSource("_F_Cm_EqGeGt_V_2S_4S_")] uint opcodes,
+                                        [Values(0u)]     uint rd,
+                                        [Values(1u, 0u)] uint rn,
+                                        [Values(2u, 0u)] uint rm,
+                                        [ValueSource("_2S_F_")] ulong z,
+                                        [ValueSource("_2S_F_")] ulong a,
+                                        [ValueSource("_2S_F_")] ulong b,
+                                        [Values(0b0u, 0b1u)] uint q) // <2S, 4S>
+        {
+            opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcodes |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(a, a * q);
+            Vector128<float> v2 = MakeVectorE0E1(b, b * q);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Cm_EqGeGt_V_2D([ValueSource("_F_Cm_EqGeGt_V_2D_")] uint opcodes,
+                                     [Values(0u)]     uint rd,
+                                     [Values(1u, 0u)] uint rn,
+                                     [Values(2u, 0u)] uint rm,
+                                     [ValueSource("_1D_F_")] ulong z,
+                                     [ValueSource("_1D_F_")] ulong a,
+                                     [ValueSource("_1D_F_")] ulong b)
+        {
+            opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(a, a);
+            Vector128<float> v2 = MakeVectorE0E1(b, b);
+
+            int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+            int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+        }
+
+        [Test, Pairwise] [Explicit]
         public void F_Cmp_Cmpe_S_S([ValueSource("_F_Cmp_Cmpe_S_S_")] uint opcodes,
                                    [ValueSource("_1S_F_")] ulong a,
                                    [ValueSource("_1S_F_")] ulong b)
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs b/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
index c9c4c1ed..f026158c 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
@@ -50,6 +50,33 @@ namespace Ryujinx.Tests.Cpu
 #endregion
 
 #region "ValueSource (Opcodes)"
+        private static uint[] _SU_Shll_V_8B8H_16B8H_()
+        {
+            return new uint[]
+            {
+                0x0F08A400u, // SSHLL V0.8H, V0.8B, #0
+                0x2F08A400u  // USHLL V0.8H, V0.8B, #0
+            };
+        }
+
+        private static uint[] _SU_Shll_V_4H4S_8H4S_()
+        {
+            return new uint[]
+            {
+                0x0F10A400u, // SSHLL V0.4S, V0.4H, #0
+                0x2F10A400u  // USHLL V0.4S, V0.4H, #0
+            };
+        }
+
+        private static uint[] _SU_Shll_V_2S2D_4S2D_()
+        {
+            return new uint[]
+            {
+                0x0F20A400u, // SSHLL V0.2D, V0.2S, #0
+                0x2F20A400u  // USHLL V0.2D, V0.2S, #0
+            };
+        }
+
         private static uint[] _ShrImm_S_D_()
         {
             return new uint[]
@@ -345,6 +372,75 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Pairwise]
+        public void SU_Shll_V_8B8H_16B8H([ValueSource("_SU_Shll_V_8B8H_16B8H_")] uint opcodes,
+                                         [Values(0u)]     uint rd,
+                                         [Values(1u, 0u)] uint rn,
+                                         [ValueSource("_8B_")] [Random(RndCnt)] ulong z,
+                                         [ValueSource("_8B_")] [Random(RndCnt)] ulong a,
+                                         [Range(0u, 7u)] uint shift,
+                                         [Values(0b0u, 0b1u)] uint q) // <8B8H, 16B8H>
+        {
+            uint immHb = (8 + shift) & 0x7F;
+
+            opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcodes |= (immHb << 16);
+            opcodes |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise]
+        public void SU_Shll_V_4H4S_8H4S([ValueSource("_SU_Shll_V_4H4S_8H4S_")] uint opcodes,
+                                        [Values(0u)]     uint rd,
+                                        [Values(1u, 0u)] uint rn,
+                                        [ValueSource("_4H_")] [Random(RndCnt)] ulong z,
+                                        [ValueSource("_4H_")] [Random(RndCnt)] ulong a,
+                                        [Range(0u, 15u)] uint shift,
+                                        [Values(0b0u, 0b1u)] uint q) // <4H4S, 8H4S>
+        {
+            uint immHb = (16 + shift) & 0x7F;
+
+            opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcodes |= (immHb << 16);
+            opcodes |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise]
+        public void SU_Shll_V_2S2D_4S2D([ValueSource("_SU_Shll_V_2S2D_4S2D_")] uint opcodes,
+                                        [Values(0u)]     uint rd,
+                                        [Values(1u, 0u)] uint rn,
+                                        [ValueSource("_2S_")] [Random(RndCnt)] ulong z,
+                                        [ValueSource("_2S_")] [Random(RndCnt)] ulong a,
+                                        [Range(0u, 31u)] uint shift,
+                                        [Values(0b0u, 0b1u)] uint q) // <2S2D, 4S2D>
+        {
+            uint immHb = (32 + shift) & 0x7F;
+
+            opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcodes |= (immHb << 16);
+            opcodes |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise]
         public void ShrImm_S_D([ValueSource("_ShrImm_S_D_")] uint opcodes,
                                [Values(0u)]     uint rd,
                                [Values(1u, 0u)] uint rn,