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Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdReg.cs')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdReg.cs168
1 files changed, 151 insertions, 17 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
index cceb8b10..8d2f4e9a 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
@@ -206,6 +206,7 @@ namespace Ryujinx.Tests.Cpu
{
return new uint[]
{
+ 0x7EA2D420u, // FABD S0, S1, S2
0x1E222820u, // FADD S0, S1, S2
0x1E221820u, // FDIV S0, S1, S2
0x1E220820u, // FMUL S0, S1, S2
@@ -218,6 +219,7 @@ namespace Ryujinx.Tests.Cpu
{
return new uint[]
{
+ 0x7EE2D420u, // FABD D0, D1, D2
0x1E622820u, // FADD D0, D1, D2
0x1E621820u, // FDIV D0, D1, D2
0x1E620820u, // FMUL D0, D1, D2
@@ -226,11 +228,13 @@ namespace Ryujinx.Tests.Cpu
};
}
- private static uint[] _F_Add_Div_Mul_Mulx_Sub_V_2S_4S_()
+ private static uint[] _F_Add_Div_Mul_Mulx_Sub_P_V_2S_4S_()
{
return new uint[]
{
+ 0x2EA0D400u, // FABD V0.2S, V0.2S, V0.2S
0x0E20D400u, // FADD V0.2S, V0.2S, V0.2S
+ 0x2E20D400u, // FADDP V0.2S, V0.2S, V0.2S
0x2E20FC00u, // FDIV V0.2S, V0.2S, V0.2S
0x2E20DC00u, // FMUL V0.2S, V0.2S, V0.2S
0x0E20DC00u, // FMULX V0.2S, V0.2S, V0.2S
@@ -238,11 +242,13 @@ namespace Ryujinx.Tests.Cpu
};
}
- private static uint[] _F_Add_Div_Mul_Mulx_Sub_V_2D_()
+ private static uint[] _F_Add_Div_Mul_Mulx_Sub_P_V_2D_()
{
return new uint[]
{
+ 0x6EE0D400u, // FABD V0.2D, V0.2D, V0.2D
0x4E60D400u, // FADD V0.2D, V0.2D, V0.2D
+ 0x6E60D400u, // FADDP V0.2D, V0.2D, V0.2D
0x6E60FC00u, // FDIV V0.2D, V0.2D, V0.2D
0x6E60DC00u, // FMUL V0.2D, V0.2D, V0.2D
0x4E60DC00u, // FMULX V0.2D, V0.2D, V0.2D
@@ -250,6 +256,46 @@ namespace Ryujinx.Tests.Cpu
};
}
+ private static uint[] _F_Cm_EqGeGt_S_S_()
+ {
+ return new uint[]
+ {
+ 0x5E22E420u, // FCMEQ S0, S1, S2
+ 0x7E22E420u, // FCMGE S0, S1, S2
+ 0x7EA2E420u // FCMGT S0, S1, S2
+ };
+ }
+
+ private static uint[] _F_Cm_EqGeGt_S_D_()
+ {
+ return new uint[]
+ {
+ 0x5E62E420u, // FCMEQ D0, D1, D2
+ 0x7E62E420u, // FCMGE D0, D1, D2
+ 0x7EE2E420u // FCMGT D0, D1, D2
+ };
+ }
+
+ private static uint[] _F_Cm_EqGeGt_V_2S_4S_()
+ {
+ return new uint[]
+ {
+ 0x0E20E400u, // FCMEQ V0.2S, V0.2S, V0.2S
+ 0x2E20E400u, // FCMGE V0.2S, V0.2S, V0.2S
+ 0x2EA0E400u // FCMGT V0.2S, V0.2S, V0.2S
+ };
+ }
+
+ private static uint[] _F_Cm_EqGeGt_V_2D_()
+ {
+ return new uint[]
+ {
+ 0x4E60E400u, // FCMEQ V0.2D, V0.2D, V0.2D
+ 0x6E60E400u, // FCMGE V0.2D, V0.2D, V0.2D
+ 0x6EE0E400u // FCMGT V0.2D, V0.2D, V0.2D
+ };
+ }
+
private static uint[] _F_Cmp_Cmpe_S_S_()
{
return new uint[]
@@ -1285,14 +1331,14 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
- public void F_Add_Div_Mul_Mulx_Sub_V_2S_4S([ValueSource("_F_Add_Div_Mul_Mulx_Sub_V_2S_4S_")] uint opcodes,
- [Values(0u)] uint rd,
- [Values(1u, 0u)] uint rn,
- [Values(2u, 0u)] uint rm,
- [ValueSource("_2S_F_")] ulong z,
- [ValueSource("_2S_F_")] ulong a,
- [ValueSource("_2S_F_")] ulong b,
- [Values(0b0u, 0b1u)] uint q) // <2S, 4S>
+ public void F_Add_Div_Mul_Mulx_Sub_P_V_2S_4S([ValueSource("_F_Add_Div_Mul_Mulx_Sub_P_V_2S_4S_")] uint opcodes,
+ [Values(0u)] uint rd,
+ [Values(1u, 0u)] uint rn,
+ [Values(2u, 0u)] uint rm,
+ [ValueSource("_2S_F_")] ulong z,
+ [ValueSource("_2S_F_")] ulong a,
+ [ValueSource("_2S_F_")] ulong b,
+ [Values(0b0u, 0b1u)] uint q) // <2S, 4S>
{
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= ((q & 1) << 30);
@@ -1312,13 +1358,13 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
- public void F_Add_Div_Mul_Mulx_Sub_V_2D([ValueSource("_F_Add_Div_Mul_Mulx_Sub_V_2D_")] uint opcodes,
- [Values(0u)] uint rd,
- [Values(1u, 0u)] uint rn,
- [Values(2u, 0u)] uint rm,
- [ValueSource("_1D_F_")] ulong z,
- [ValueSource("_1D_F_")] ulong a,
- [ValueSource("_1D_F_")] ulong b)
+ public void F_Add_Div_Mul_Mulx_Sub_P_V_2D([ValueSource("_F_Add_Div_Mul_Mulx_Sub_P_V_2D_")] uint opcodes,
+ [Values(0u)] uint rd,
+ [Values(1u, 0u)] uint rn,
+ [Values(2u, 0u)] uint rm,
+ [ValueSource("_1D_F_")] ulong z,
+ [ValueSource("_1D_F_")] ulong a,
+ [ValueSource("_1D_F_")] ulong b)
{
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -1337,6 +1383,94 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise] [Explicit]
+ public void F_Cm_EqGeGt_S_S([ValueSource("_F_Cm_EqGeGt_S_S_")] uint opcodes,
+ [ValueSource("_1S_F_")] ulong a,
+ [ValueSource("_1S_F_")] ulong b)
+ {
+ ulong z = TestContext.CurrentContext.Random.NextULong();
+ Vector128<float> v0 = MakeVectorE0E1(z, z);
+ Vector128<float> v1 = MakeVectorE0(a);
+ Vector128<float> v2 = MakeVectorE0(b);
+
+ int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+ int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+ SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
+
+ CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+ }
+
+ [Test, Pairwise] [Explicit]
+ public void F_Cm_EqGeGt_S_D([ValueSource("_F_Cm_EqGeGt_S_D_")] uint opcodes,
+ [ValueSource("_1D_F_")] ulong a,
+ [ValueSource("_1D_F_")] ulong b)
+ {
+ ulong z = TestContext.CurrentContext.Random.NextULong();
+ Vector128<float> v0 = MakeVectorE1(z);
+ Vector128<float> v1 = MakeVectorE0(a);
+ Vector128<float> v2 = MakeVectorE0(b);
+
+ int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+ int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+ SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
+
+ CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+ }
+
+ [Test, Pairwise] [Explicit]
+ public void F_Cm_EqGeGt_V_2S_4S([ValueSource("_F_Cm_EqGeGt_V_2S_4S_")] uint opcodes,
+ [Values(0u)] uint rd,
+ [Values(1u, 0u)] uint rn,
+ [Values(2u, 0u)] uint rm,
+ [ValueSource("_2S_F_")] ulong z,
+ [ValueSource("_2S_F_")] ulong a,
+ [ValueSource("_2S_F_")] ulong b,
+ [Values(0b0u, 0b1u)] uint q) // <2S, 4S>
+ {
+ opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
+ opcodes |= ((q & 1) << 30);
+
+ Vector128<float> v0 = MakeVectorE0E1(z, z);
+ Vector128<float> v1 = MakeVectorE0E1(a, a * q);
+ Vector128<float> v2 = MakeVectorE0E1(b, b * q);
+
+ int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+ int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+ SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
+
+ CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+ }
+
+ [Test, Pairwise] [Explicit]
+ public void F_Cm_EqGeGt_V_2D([ValueSource("_F_Cm_EqGeGt_V_2D_")] uint opcodes,
+ [Values(0u)] uint rd,
+ [Values(1u, 0u)] uint rn,
+ [Values(2u, 0u)] uint rm,
+ [ValueSource("_1D_F_")] ulong z,
+ [ValueSource("_1D_F_")] ulong a,
+ [ValueSource("_1D_F_")] ulong b)
+ {
+ opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
+
+ Vector128<float> v0 = MakeVectorE0E1(z, z);
+ Vector128<float> v1 = MakeVectorE0E1(a, a);
+ Vector128<float> v2 = MakeVectorE0E1(b, b);
+
+ int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
+
+ int fpcr = rnd & (1 << (int)Fpcr.Fz);
+
+ SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, fpcr: fpcr);
+
+ CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
+ }
+
+ [Test, Pairwise] [Explicit]
public void F_Cmp_Cmpe_S_S([ValueSource("_F_Cmp_Cmpe_S_S_")] uint opcodes,
[ValueSource("_1S_F_")] ulong a,
[ValueSource("_1S_F_")] ulong b)
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-08 04:57:38 +0000