diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2019-03-13 09:23:52 +0100 |
|---|---|---|
| committer | jduncanator <1518948+jduncanator@users.noreply.github.com> | 2019-03-13 19:23:52 +1100 |
| commit | 1bef70c068f8aeb6a3a518b8ca635de19122da14 (patch) | |
| tree | 84d3ead95523f4803de1e6288f38ad45d6039005 /Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs | |
| parent | a0aecd1ff85437890bb6a86fcc71fc90e80a4d24 (diff) | |
Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614)
* Update CountLeadingZeros().
* Remove obsolete Tests.
* Follow-up.
* Follow-up.
* Follow-up.
* Add Mla_V, Mls_V & Mul_V Tests.
* Update PackageReferences.
* Remove EmitLd/Stvectmp2().
* Remove Dup. Nits.
* Remove EmitLd/Stvectmp2() & Dup; nits.
* Remove Tmp stuff & Dup; rework Fcvtz() as Fcvtn().
* Remove Tmp stuff, EmitLd/Stvectmp2() & Dup. Nits.
* Add (R)shrn_V Sse opt.; add "Part" & "Shift" opt..
Remove Tmp stuff; remove Dup.
Nits.
* Add Mla/Mls/Mul_V Sse opt.. Add "Part" opt..
Remove EmitLd/Stvectmp2(), remove Dup.
Nits.
* Nits.
* Nits.
* Nit.
* Add "Part" opt.. Nit.
* Nit.
* Nit.
* Add Cmhi_V & Cmhs_V Sse opt..
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs index 2f8604eb..63e0bda8 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs @@ -8,26 +8,6 @@ namespace Ryujinx.Tests.Cpu { public class CpuTestSimdArithmetic : CpuTest { - [TestCase(0x00000000u, 0x7F800000u)] - [TestCase(0x80000000u, 0xFF800000u)] - [TestCase(0x00FFF000u, 0x7E000000u)] - [TestCase(0x41200000u, 0x3DCC8000u)] - [TestCase(0xC1200000u, 0xBDCC8000u)] - [TestCase(0x001FFFFFu, 0x7F800000u)] - [TestCase(0x007FF000u, 0x7E800000u)] - public void Frecpe_S(uint a, uint result) - { - uint opcode = 0x5EA1D820; // FRECPE S0, S1 - - Vector128<float> v1 = MakeVectorE0(a); - - CpuThreadState threadState = SingleOpcode(opcode, v1: v1); - - Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(result)); - - CompareAgainstUnicorn(); - } - [TestCase(0x3FE66666u, false, 0x40000000u)] [TestCase(0x3F99999Au, false, 0x3F800000u)] [TestCase(0x404CCCCDu, false, 0x40400000u)] @@ -601,19 +581,5 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - - [TestCase(0x41200000u, 0x3EA18000u)] - public void Frsqrte_S(uint a, uint result) - { - uint opcode = 0x7EA1D820; // FRSQRTE S0, S1 - - Vector128<float> v1 = MakeVectorE0(a); - - CpuThreadState threadState = SingleOpcode(opcode, v1: v1); - - Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(result)); - - CompareAgainstUnicorn(); - } } } |