diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-08-27 08:44:01 +0200 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-08-27 03:44:01 -0300 |
| commit | 68300368d7fd4ee49ced471beafad4d64c3e7709 (patch) | |
| tree | e96e0676472ca74d67d229bac1e8c16c4b66fb37 /Ryujinx.Tests/Cpu/CpuTestSimd.cs | |
| parent | 43c4e7c78d98b09e8dc51e3450396cd99b2b3a92 (diff) | |
Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdCrypto.cs
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimd.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimd.cs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs index 68e2d721..d1832ce8 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs @@ -1245,11 +1245,11 @@ namespace Ryujinx.Tests.Cpu }); } - [Test, Explicit, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")] // 1250 tests. + [Test, Pairwise, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")] public void Sha256su0_V([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, - [Random(5)] ulong Z0, [Random(5)] ulong Z1, - [Random(5)] ulong A0, [Random(5)] ulong A1) + [Random(RndCnt * 2)] ulong Z0, [Random(RndCnt * 2)] ulong Z1, + [Random(RndCnt * 2)] ulong A0, [Random(RndCnt * 2)] ulong A1) { uint Opcode = 0x5E282800; // SHA256SU0 V0.4S, V0.4S Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); |