From 68300368d7fd4ee49ced471beafad4d64c3e7709 Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Mon, 27 Aug 2018 08:44:01 +0200 Subject: Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380) * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdCrypto.cs --- Ryujinx.Tests/Cpu/CpuTestSimd.cs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Ryujinx.Tests/Cpu/CpuTestSimd.cs') diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs index 68e2d721..d1832ce8 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs @@ -1245,11 +1245,11 @@ namespace Ryujinx.Tests.Cpu }); } - [Test, Explicit, Description("SHA256SU0 .4S, .4S")] // 1250 tests. + [Test, Pairwise, Description("SHA256SU0 .4S, .4S")] public void Sha256su0_V([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, - [Random(5)] ulong Z0, [Random(5)] ulong Z1, - [Random(5)] ulong A0, [Random(5)] ulong A1) + [Random(RndCnt * 2)] ulong Z0, [Random(RndCnt * 2)] ulong Z1, + [Random(RndCnt * 2)] ulong A0, [Random(RndCnt * 2)] ulong A1) { uint Opcode = 0x5E282800; // SHA256SU0 V0.4S, V0.4S Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); -- cgit v1.2.3