aboutsummaryrefslogtreecommitdiff
path: root/Ryujinx.Graphics.Shader/Translation
diff options
context:
space:
mode:
authorgdkchan <gab.dark.100@gmail.com>2020-10-13 00:44:55 -0300
committerGitHub <noreply@github.com>2020-10-13 14:44:55 +1100
commitd36c4bfba5a849b3efebe72ca44e66c9714b7e60 (patch)
tree610ba7efa7f717f1e4cbc40f54dd898403697d44 /Ryujinx.Graphics.Shader/Translation
parent6a51b628f910deb6356974c2eb6fb2dba1dfdb34 (diff)
Fix output component register on pixel shaders (#1613)
* Fix output component register on pixel shaders * Clean up usings * Do not advance if no component is enabled for the target, this keeps the previous behavior
Diffstat (limited to 'Ryujinx.Graphics.Shader/Translation')
-rw-r--r--Ryujinx.Graphics.Shader/Translation/EmitterContext.cs12
1 files changed, 6 insertions, 6 deletions
diff --git a/Ryujinx.Graphics.Shader/Translation/EmitterContext.cs b/Ryujinx.Graphics.Shader/Translation/EmitterContext.cs
index 79685154..c5ebe9e7 100644
--- a/Ryujinx.Graphics.Shader/Translation/EmitterContext.cs
+++ b/Ryujinx.Graphics.Shader/Translation/EmitterContext.cs
@@ -1,4 +1,3 @@
-using Ryujinx.Common;
using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using System.Collections.Generic;
@@ -85,7 +84,7 @@ namespace Ryujinx.Graphics.Shader.Translation
this.Copy(dest, src);
}
- int regIndex = 0;
+ int regIndexBase = 0;
for (int rtIndex = 0; rtIndex < 8; rtIndex++)
{
@@ -100,7 +99,7 @@ namespace Ryujinx.Graphics.Shader.Translation
int fragmentOutputColorAttr = AttributeConsts.FragmentOutputColorBase + rtIndex * 16;
- Operand src = Register(regIndex, RegisterType.Gpr);
+ Operand src = Register(regIndexBase + component, RegisterType.Gpr);
// Perform B <-> R swap if needed, for BGRA formats (not supported on OpenGL).
if (component == 0 || component == 2)
@@ -125,11 +124,12 @@ namespace Ryujinx.Graphics.Shader.Translation
{
this.Copy(Attribute(fragmentOutputColorAttr + component * 4), src);
}
-
- regIndex++;
}
- regIndex = BitUtils.AlignUp(regIndex, 4);
+ if (target.Enabled)
+ {
+ regIndexBase += 4;
+ }
}
}
}