diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2018-03-30 15:55:28 -0300 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-03-30 15:55:28 -0300 |
| commit | f42f39fd90a8e43531ba178ad2caaafe79ce94ae (patch) | |
| tree | ed4ff2c913f33d88e11ae1f3ec7218ca2eee8ab8 /ChocolArm64 | |
| parent | 9b6fa1f89e7e1cac47e28bb64e626dff5263e953 (diff) | |
Add UADDL instruction
Diffstat (limited to 'ChocolArm64')
| -rw-r--r-- | ChocolArm64/AOpCodeTable.cs | 1 | ||||
| -rw-r--r-- | ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index 0dca92d7..33df4367 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -285,6 +285,7 @@ namespace ChocolArm64 Set("01111110xx1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_S, typeof(AOpCodeSimdReg)); Set("0>101110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_V, typeof(AOpCodeSimdReg)); Set("0x001110000xxxxx0xx000xxxxxxxxxx", AInstEmit.Tbl_V, typeof(AOpCodeSimdTbl)); + Set("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg)); Set("001011100x110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd)); Set("01101110<<110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd)); Set("0x101110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Uaddw_V, typeof(AOpCodeSimdReg)); diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs index cd4d31f9..52148bce 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs @@ -546,6 +546,11 @@ namespace ChocolArm64.Instruction EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub)); } + public static void Uaddl_V(AILEmitterCtx Context) + { + EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Add)); + } + public static void Uaddlv_V(AILEmitterCtx Context) { AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; |
