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authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2018-08-27 08:44:01 +0200
committergdkchan <gab.dark.100@gmail.com>2018-08-27 03:44:01 -0300
commit68300368d7fd4ee49ced471beafad4d64c3e7709 (patch)
treee96e0676472ca74d67d229bac1e8c16c4b66fb37 /ChocolArm64
parent43c4e7c78d98b09e8dc51e3450396cd99b2b3a92 (diff)
Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)
* Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdCrypto.cs
Diffstat (limited to 'ChocolArm64')
-rw-r--r--ChocolArm64/AOpCodeTable.cs5
-rw-r--r--ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs78
2 files changed, 74 insertions, 9 deletions
diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs
index dc8cfc08..bf030314 100644
--- a/ChocolArm64/AOpCodeTable.cs
+++ b/ChocolArm64/AOpCodeTable.cs
@@ -374,10 +374,12 @@ namespace ChocolArm64
SetA64("01011110000xxxxx010100xxxxxxxxxx", AInstEmit.Sha256h2_V, typeof(AOpCodeSimdReg));
SetA64("0101111000101000001010xxxxxxxxxx", AInstEmit.Sha256su0_V, typeof(AOpCodeSimd));
SetA64("01011110000xxxxx011000xxxxxxxxxx", AInstEmit.Sha256su1_V, typeof(AOpCodeSimdReg));
+ SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Shadd_V, typeof(AOpCodeSimdReg));
SetA64("010111110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm));
SetA64("0x0011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
SetA64("0x101110<<100001001110xxxxxxxxxx", AInstEmit.Shll_V, typeof(AOpCodeSimd));
SetA64("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V, typeof(AOpCodeSimdShImm));
+ SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Shsub_V, typeof(AOpCodeSimdReg));
SetA64("0x1011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Sli_V, typeof(AOpCodeSimdShImm));
SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Smax_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Smaxp_V, typeof(AOpCodeSimdReg));
@@ -407,6 +409,7 @@ namespace ChocolArm64
SetA64("0x001110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_V, typeof(AOpCodeSimd));
SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S, typeof(AOpCodeSimd));
SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V, typeof(AOpCodeSimd));
+ SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Srhadd_V, typeof(AOpCodeSimdReg));
SetA64("0x00111100>>>xxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
SetA64("0100111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg));
@@ -449,6 +452,7 @@ namespace ChocolArm64
SetA64("011111100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_S, typeof(AOpCodeSimd));
SetA64("0x1011100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_V, typeof(AOpCodeSimd));
SetA64("0x101110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Uhadd_V, typeof(AOpCodeSimdReg));
+ SetA64("0x101110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Uhsub_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Umax_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Umaxp_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Umin_V, typeof(AOpCodeSimdReg));
@@ -461,6 +465,7 @@ namespace ChocolArm64
SetA64("0>101110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_V, typeof(AOpCodeSimdReg));
SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd));
SetA64("0x101110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_V, typeof(AOpCodeSimd));
+ SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Urhadd_V, typeof(AOpCodeSimdReg));
SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V, typeof(AOpCodeSimdReg));
SetA64("0x10111100>>>xxx101001xxxxxxxxxx", AInstEmit.Ushll_V, typeof(AOpCodeSimdShImm));
SetA64("0111111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_S, typeof(AOpCodeSimdShImm));
diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
index 92da9ff9..1e4002a0 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
@@ -1042,6 +1042,28 @@ namespace ChocolArm64.Instruction
EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
}
+ public static void Shadd_V(AILEmitterCtx Context)
+ {
+ EmitVectorBinaryOpSx(Context, () =>
+ {
+ Context.Emit(OpCodes.Add);
+
+ Context.Emit(OpCodes.Ldc_I4_1);
+ Context.Emit(OpCodes.Shr);
+ });
+ }
+
+ public static void Shsub_V(AILEmitterCtx Context)
+ {
+ EmitVectorBinaryOpSx(Context, () =>
+ {
+ Context.Emit(OpCodes.Sub);
+
+ Context.Emit(OpCodes.Ldc_I4_1);
+ Context.Emit(OpCodes.Shr);
+ });
+ }
+
public static void Smax_V(AILEmitterCtx Context)
{
Type[] Types = new Type[] { typeof(long), typeof(long) };
@@ -1181,6 +1203,20 @@ namespace ChocolArm64.Instruction
EmitVectorSaturatingNarrowOpSxZx(Context, () => { });
}
+ public static void Srhadd_V(AILEmitterCtx Context)
+ {
+ EmitVectorBinaryOpSx(Context, () =>
+ {
+ Context.Emit(OpCodes.Add);
+
+ Context.Emit(OpCodes.Ldc_I4_1);
+ Context.Emit(OpCodes.Add);
+
+ Context.Emit(OpCodes.Ldc_I4_1);
+ Context.Emit(OpCodes.Shr);
+ });
+ }
+
public static void Ssubw_V(AILEmitterCtx Context)
{
EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
@@ -1303,44 +1339,54 @@ namespace ChocolArm64.Instruction
{
Context.Emit(OpCodes.Add);
- Context.EmitLdc_I4(1);
+ Context.Emit(OpCodes.Ldc_I4_1);
+ Context.Emit(OpCodes.Shr_Un);
+ });
+ }
+ public static void Uhsub_V(AILEmitterCtx Context)
+ {
+ EmitVectorBinaryOpZx(Context, () =>
+ {
+ Context.Emit(OpCodes.Sub);
+
+ Context.Emit(OpCodes.Ldc_I4_1);
Context.Emit(OpCodes.Shr_Un);
});
}
- public static void Umin_V(AILEmitterCtx Context)
+ public static void Umax_V(AILEmitterCtx Context)
{
Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
- MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
+ MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Max), Types);
EmitVectorBinaryOpZx(Context, () => Context.EmitCall(MthdInfo));
}
- public static void Uminp_V(AILEmitterCtx Context)
+ public static void Umaxp_V(AILEmitterCtx Context)
{
Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
- MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
+ MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Max), Types);
EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
}
- public static void Umax_V(AILEmitterCtx Context)
+ public static void Umin_V(AILEmitterCtx Context)
{
Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
- MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Max), Types);
+ MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
EmitVectorBinaryOpZx(Context, () => Context.EmitCall(MthdInfo));
}
- public static void Umaxp_V(AILEmitterCtx Context)
+ public static void Uminp_V(AILEmitterCtx Context)
{
Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
- MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Max), Types);
+ MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
}
@@ -1380,6 +1426,20 @@ namespace ChocolArm64.Instruction
EmitVectorSaturatingNarrowOpZxZx(Context, () => { });
}
+ public static void Urhadd_V(AILEmitterCtx Context)
+ {
+ EmitVectorBinaryOpZx(Context, () =>
+ {
+ Context.Emit(OpCodes.Add);
+
+ Context.Emit(OpCodes.Ldc_I4_1);
+ Context.Emit(OpCodes.Add);
+
+ Context.Emit(OpCodes.Ldc_I4_1);
+ Context.Emit(OpCodes.Shr_Un);
+ });
+ }
+
public static void Usqadd_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate);