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authorgdkchan <gab.dark.100@gmail.com>2019-01-29 13:06:11 -0300
committerGitHub <noreply@github.com>2019-01-29 13:06:11 -0300
commitc1bdf19061ec679aa3c69eda2a41337e3e809014 (patch)
treef3813b8df8ff8dd1fbf73fd085893b0df21850dc /ChocolArm64/State/PState.cs
parent8f7fcede7fa98c605925dc7b9316940960543bf1 (diff)
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
Diffstat (limited to 'ChocolArm64/State/PState.cs')
-rw-r--r--ChocolArm64/State/PState.cs17
1 files changed, 7 insertions, 10 deletions
diff --git a/ChocolArm64/State/PState.cs b/ChocolArm64/State/PState.cs
index aef5f53b..053a5357 100644
--- a/ChocolArm64/State/PState.cs
+++ b/ChocolArm64/State/PState.cs
@@ -6,22 +6,19 @@ namespace ChocolArm64.State
enum PState
{
TBit = 5,
+ EBit = 9,
VBit = 28,
CBit = 29,
ZBit = 30,
NBit = 31,
- T = 1 << TBit,
+ TMask = 1 << TBit,
+ EMask = 1 << EBit,
- V = 1 << VBit,
- C = 1 << CBit,
- Z = 1 << ZBit,
- N = 1 << NBit,
-
- Nz = N | Z,
- Cv = C | V,
-
- Nzcv = Nz | Cv
+ VMask = 1 << VBit,
+ CMask = 1 << CBit,
+ ZMask = 1 << ZBit,
+ NMask = 1 << NBit
}
}