From c1bdf19061ec679aa3c69eda2a41337e3e809014 Mon Sep 17 00:00:00 2001 From: gdkchan Date: Tue, 29 Jan 2019 13:06:11 -0300 Subject: Implement some ARM32 memory instructions and CMP (#565) * Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table --- ChocolArm64/State/PState.cs | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) (limited to 'ChocolArm64/State/PState.cs') diff --git a/ChocolArm64/State/PState.cs b/ChocolArm64/State/PState.cs index aef5f53b..053a5357 100644 --- a/ChocolArm64/State/PState.cs +++ b/ChocolArm64/State/PState.cs @@ -6,22 +6,19 @@ namespace ChocolArm64.State enum PState { TBit = 5, + EBit = 9, VBit = 28, CBit = 29, ZBit = 30, NBit = 31, - T = 1 << TBit, + TMask = 1 << TBit, + EMask = 1 << EBit, - V = 1 << VBit, - C = 1 << CBit, - Z = 1 << ZBit, - N = 1 << NBit, - - Nz = N | Z, - Cv = C | V, - - Nzcv = Nz | Cv + VMask = 1 << VBit, + CMask = 1 << CBit, + ZMask = 1 << ZBit, + NMask = 1 << NBit } } -- cgit v1.2.3