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authorgdkchan <gab.dark.100@gmail.com>2018-03-30 16:46:00 -0300
committergdkchan <gab.dark.100@gmail.com>2018-03-30 16:46:00 -0300
commit76ac31add656c71f9cfb3307f5863cc98c8d1467 (patch)
tree0e84580120d7e81a9e8ba033c778bfa15cc4cc14 /ChocolArm64/Instruction
parent19b83445683cf9cfcf9e3d27596ab030eb08353c (diff)
Add BIT instruction
Diffstat (limited to 'ChocolArm64/Instruction')
-rw-r--r--ChocolArm64/Instruction/AInstEmitSimdLogical.cs15
1 files changed, 15 insertions, 0 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
index 8fd8ea4d..967c3d30 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
@@ -34,6 +34,16 @@ namespace ChocolArm64.Instruction
public static void Bif_V(AILEmitterCtx Context)
{
+ EmitBitBif(Context, true);
+ }
+
+ public static void Bit_V(AILEmitterCtx Context)
+ {
+ EmitBitBif(Context, false);
+ }
+
+ public static void EmitBitBif(AILEmitterCtx Context, bool NotRm)
+ {
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
@@ -47,6 +57,11 @@ namespace ChocolArm64.Instruction
EmitVectorExtractZx(Context, Op.Rm, Index, Op.Size);
+ if (NotRm)
+ {
+ Context.Emit(OpCodes.Not);
+ }
+
Context.Emit(OpCodes.And);
EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);