diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2018-03-30 16:46:00 -0300 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-03-30 16:46:00 -0300 |
| commit | 76ac31add656c71f9cfb3307f5863cc98c8d1467 (patch) | |
| tree | 0e84580120d7e81a9e8ba033c778bfa15cc4cc14 | |
| parent | 19b83445683cf9cfcf9e3d27596ab030eb08353c (diff) | |
Add BIT instruction
| -rw-r--r-- | ChocolArm64/AOpCodeTable.cs | 1 | ||||
| -rw-r--r-- | ChocolArm64/Instruction/AInstEmitSimdLogical.cs | 15 |
2 files changed, 16 insertions, 0 deletions
diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index c2929d9b..0d3fa296 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -141,6 +141,7 @@ namespace ChocolArm64 Set("0x001110011xxxxx000111xxxxxxxxxx", AInstEmit.Bic_V, typeof(AOpCodeSimdReg)); Set("0x10111100000xxx<<x101xxxxxxxxxx", AInstEmit.Bic_Vi, typeof(AOpCodeSimdImm)); Set("0x101110111xxxxx000111xxxxxxxxxx", AInstEmit.Bif_V, typeof(AOpCodeSimdReg)); + Set("0x101110101xxxxx000111xxxxxxxxxx", AInstEmit.Bit_V, typeof(AOpCodeSimdReg)); Set("0x101110011xxxxx000111xxxxxxxxxx", AInstEmit.Bsl_V, typeof(AOpCodeSimdReg)); Set("0>101110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimdReg)); Set("0>001110<<100000100110xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimd)); diff --git a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs index 8fd8ea4d..967c3d30 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs @@ -34,6 +34,16 @@ namespace ChocolArm64.Instruction public static void Bif_V(AILEmitterCtx Context) { + EmitBitBif(Context, true); + } + + public static void Bit_V(AILEmitterCtx Context) + { + EmitBitBif(Context, false); + } + + public static void EmitBitBif(AILEmitterCtx Context, bool NotRm) + { AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; int Bytes = Context.CurrOp.GetBitsCount() >> 3; @@ -47,6 +57,11 @@ namespace ChocolArm64.Instruction EmitVectorExtractZx(Context, Op.Rm, Index, Op.Size); + if (NotRm) + { + Context.Emit(OpCodes.Not); + } + Context.Emit(OpCodes.And); EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size); |
