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authorgdkchan <gab.dark.100@gmail.com>2018-03-02 19:21:54 -0300
committergdkchan <gab.dark.100@gmail.com>2018-03-02 19:23:38 -0300
commitf39a864050589ac7e757a9d72b46ac693125b382 (patch)
treeba56ae59aabca61e0efd4d68ce227b93a6b78477 /ChocolArm64/Instruction/AInstEmitSimdMove.cs
parent1d71e33171f78fb40b097108fbd5915f18c608c4 (diff)
Add EXT, CMTST (vector) and UMULL (vector) instructions
Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdMove.cs')
-rw-r--r--ChocolArm64/Instruction/AInstEmitSimdMove.cs25
1 files changed, 25 insertions, 0 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdMove.cs b/ChocolArm64/Instruction/AInstEmitSimdMove.cs
index aabb8f34..a4e53370 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdMove.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdMove.cs
@@ -57,6 +57,31 @@ namespace ChocolArm64.Instruction
}
}
+ public static void Ext_V(AILEmitterCtx Context)
+ {
+ AOpCodeSimdExt Op = (AOpCodeSimdExt)Context.CurrOp;
+
+ int Bytes = Context.CurrOp.GetBitsCount() >> 3;
+
+ for (int Index = 0; Index < Bytes; Index++)
+ {
+ int Position = Op.Imm4 + Index;
+
+ int Reg = Position < Bytes ? Op.Rn : Op.Rm;
+
+ Position &= Bytes - 1;
+
+ EmitVectorExtractZx(Context, Reg, Position, 0);
+
+ EmitVectorInsert(Context, Op.Rd, Index, 0);
+ }
+
+ if (Op.RegisterSize == ARegisterSize.SIMD64)
+ {
+ EmitVectorZeroUpper(Context, Op.Rd);
+ }
+ }
+
public static void Fcsel_S(AILEmitterCtx Context)
{
AOpCodeSimdFcond Op = (AOpCodeSimdFcond)Context.CurrOp;