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authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2018-06-30 17:40:41 +0200
committergdkchan <gab.dark.100@gmail.com>2018-06-30 12:40:41 -0300
commit53934e88727b3d86ccb5ac08a489b28c8f7fc991 (patch)
tree39a3a5bb819b4999db6368125f345013b00ef88f /ChocolArm64/Instruction/AInstEmitSimdHelper.cs
parentedfd4bc860e05698946605c740fdb5857d64e917 (diff)
Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. (#204)
* Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update Instructions.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs
Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdHelper.cs')
-rw-r--r--ChocolArm64/Instruction/AInstEmitSimdHelper.cs5
1 files changed, 5 insertions, 0 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
index bca45649..83f6ca25 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
@@ -483,6 +483,11 @@ namespace ChocolArm64.Instruction
EmitVectorOp(Context, Emit, OperFlags.RnRm, true);
}
+ public static void EmitVectorTernaryOpSx(AILEmitterCtx Context, Action Emit)
+ {
+ EmitVectorOp(Context, Emit, OperFlags.RdRnRm, true);
+ }
+
public static void EmitVectorUnaryOpZx(AILEmitterCtx Context, Action Emit)
{
EmitVectorOp(Context, Emit, OperFlags.Rn, false);