From 53934e88727b3d86ccb5ac08a489b28c8f7fc991 Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Sat, 30 Jun 2018 17:40:41 +0200
Subject: Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V,
 Uabdl_V. Add 16 tests. (#204)

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Update Instructions.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs
---
 ChocolArm64/Instruction/AInstEmitSimdHelper.cs | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'ChocolArm64/Instruction/AInstEmitSimdHelper.cs')

diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
index bca45649..83f6ca25 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
@@ -483,6 +483,11 @@ namespace ChocolArm64.Instruction
             EmitVectorOp(Context, Emit, OperFlags.RnRm, true);
         }
 
+        public static void EmitVectorTernaryOpSx(AILEmitterCtx Context, Action Emit)
+        {
+            EmitVectorOp(Context, Emit, OperFlags.RdRnRm, true);
+        }
+
         public static void EmitVectorUnaryOpZx(AILEmitterCtx Context, Action Emit)
         {
             EmitVectorOp(Context, Emit, OperFlags.Rn, false);
-- 
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