diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2018-03-05 16:18:37 -0300 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-03-05 16:18:37 -0300 |
| commit | 59d1b2ad83385dad49cf930e826ce0693b9cee2c (patch) | |
| tree | 3a5cf63453273d8469a63c673dc3929c0d0948fa /ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs | |
| parent | 0e343a748d9dcfe50b885b8c0c5e886bc44080ac (diff) | |
Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
Diffstat (limited to 'ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs')
| -rw-r--r-- | ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs b/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs new file mode 100644 index 00000000..e61d7093 --- /dev/null +++ b/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs @@ -0,0 +1,22 @@ +using ChocolArm64.Instruction; + +namespace ChocolArm64.Decoder +{ + class AOpCodeSimdRegElemF : AOpCodeSimdReg + { + public int Index { get; private set; } + + public AOpCodeSimdRegElemF(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode) + { + if ((Size & 1) != 0) + { + Index = (OpCode >> 11) & 1; + } + else + { + Index = (OpCode >> 21) & 1 | + (OpCode >> 10) & 2; + } + } + } +}
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