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authorgdkchan <gab.dark.100@gmail.com>2018-03-05 16:18:37 -0300
committergdkchan <gab.dark.100@gmail.com>2018-03-05 16:18:37 -0300
commit59d1b2ad83385dad49cf930e826ce0693b9cee2c (patch)
tree3a5cf63453273d8469a63c673dc3929c0d0948fa /ChocolArm64/Decoder/AOpCodeSimdReg.cs
parent0e343a748d9dcfe50b885b8c0c5e886bc44080ac (diff)
Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
Diffstat (limited to 'ChocolArm64/Decoder/AOpCodeSimdReg.cs')
-rw-r--r--ChocolArm64/Decoder/AOpCodeSimdReg.cs6
1 files changed, 3 insertions, 3 deletions
diff --git a/ChocolArm64/Decoder/AOpCodeSimdReg.cs b/ChocolArm64/Decoder/AOpCodeSimdReg.cs
index 10a4aff8..702ffed1 100644
--- a/ChocolArm64/Decoder/AOpCodeSimdReg.cs
+++ b/ChocolArm64/Decoder/AOpCodeSimdReg.cs
@@ -4,9 +4,9 @@ namespace ChocolArm64.Decoder
{
class AOpCodeSimdReg : AOpCodeSimd
{
- public bool Bit3 { get; private set; }
- public int Ra { get; private set; }
- public int Rm { get; private set; }
+ public bool Bit3 { get; private set; }
+ public int Ra { get; private set; }
+ public int Rm { get; protected set; }
public AOpCodeSimdReg(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{