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| author | FICTURE7 <FICTURE7@gmail.com> | 2021-04-02 21:26:16 +0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-02 19:26:16 +0200 |
| commit | 8b3eba7e1333ca69e55e3ca85a77d3dd4205e991 (patch) | |
| tree | 6ff0fc4d2c4bc5f11afa9f154ff234a1afc78046 /ARMeilleure/IntermediateRepresentation | |
| parent | 529df341f1c00cdf6fb2ce3f1f305c2b106ab79d (diff) | |
Reduce allocation during SSA construction (#2162)
* Reduce allocation during SSA construction
* Re-trigger CI
Diffstat (limited to 'ARMeilleure/IntermediateRepresentation')
| -rw-r--r-- | ARMeilleure/IntermediateRepresentation/Operand.cs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/ARMeilleure/IntermediateRepresentation/Operand.cs b/ARMeilleure/IntermediateRepresentation/Operand.cs index b8650d5a..7b486c55 100644 --- a/ARMeilleure/IntermediateRepresentation/Operand.cs +++ b/ARMeilleure/IntermediateRepresentation/Operand.cs @@ -1,5 +1,6 @@ using System; using System.Collections.Generic; +using System.Runtime.CompilerServices; namespace ARMeilleure.IntermediateRepresentation { @@ -84,6 +85,7 @@ namespace ARMeilleure.IntermediateRepresentation return With(OperandKind.Register, type, (ulong)((int)regType << 24 | index)); } + [MethodImpl(MethodImplOptions.AggressiveInlining)] public Register GetRegister() { return new Register((int)Value & 0xffffff, (RegisterType)(Value >> 24)); |