diff options
| author | riperiperi <rhy3756547@hotmail.com> | 2020-03-13 23:29:58 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-14 10:29:58 +1100 |
| commit | dd433c1296bbd82e5e42bf8de1731a4eaadcfdb5 (patch) | |
| tree | a77472d331a7b4af4fd516a5f6de44ca7417376d /ARMeilleure/Instructions | |
| parent | ff2bac9c9042ef23437b19a32f3f2b6869cc1274 (diff) | |
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)
* Add VEOR and AES instructions.
* Add tests for crypto instructions.
* Update ValueSource name.
Diffstat (limited to 'ARMeilleure/Instructions')
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitSimdCrypto32.cs | 49 | ||||
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitSimdLogical32.cs | 12 | ||||
| -rw-r--r-- | ARMeilleure/Instructions/InstName.cs | 1 |
3 files changed, 62 insertions, 0 deletions
diff --git a/ARMeilleure/Instructions/InstEmitSimdCrypto32.cs b/ARMeilleure/Instructions/InstEmitSimdCrypto32.cs new file mode 100644 index 00000000..1cfce3ad --- /dev/null +++ b/ARMeilleure/Instructions/InstEmitSimdCrypto32.cs @@ -0,0 +1,49 @@ +using ARMeilleure.Decoders; +using ARMeilleure.IntermediateRepresentation; +using ARMeilleure.Translation; + +using static ARMeilleure.Instructions.InstEmitHelper; + +namespace ARMeilleure.Instructions +{ + partial class InstEmit32 + { + public static void Aesd_V(ArmEmitterContext context) + { + OpCode32Simd op = (OpCode32Simd)context.CurrOp; + + Operand d = GetVecA32(op.Qd); + Operand n = GetVecA32(op.Qm); + + context.Copy(d, context.Call(new _V128_V128_V128(SoftFallback.Decrypt), d, n)); + } + + public static void Aese_V(ArmEmitterContext context) + { + OpCode32Simd op = (OpCode32Simd)context.CurrOp; + + Operand d = GetVecA32(op.Qd); + Operand n = GetVecA32(op.Qm); + + context.Copy(d, context.Call(new _V128_V128_V128(SoftFallback.Encrypt), d, n)); + } + + public static void Aesimc_V(ArmEmitterContext context) + { + OpCode32Simd op = (OpCode32Simd)context.CurrOp; + + Operand n = GetVecA32(op.Qm); + + context.Copy(GetVec(op.Qd), context.Call(new _V128_V128(SoftFallback.InverseMixColumns), n)); + } + + public static void Aesmc_V(ArmEmitterContext context) + { + OpCode32Simd op = (OpCode32Simd)context.CurrOp; + + Operand n = GetVecA32(op.Qm); + + context.Copy(GetVec(op.Qd), context.Call(new _V128_V128(SoftFallback.MixColumns), n)); + } + } +} diff --git a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs index 3698f332..6505e834 100644 --- a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs @@ -55,6 +55,18 @@ namespace ARMeilleure.Instructions } } + public static void Veor_I(ArmEmitterContext context) + { + if (Optimizations.UseSse2) + { + EmitVectorBinaryOpF32(context, Intrinsic.X86Pxor, Intrinsic.X86Pxor); + } + else + { + EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseExclusiveOr(op1, op2)); + } + } + public static void Vorr_I(ArmEmitterContext context) { if (Optimizations.UseSse2) diff --git a/ARMeilleure/Instructions/InstName.cs b/ARMeilleure/Instructions/InstName.cs index 5e92da0a..e217c6ec 100644 --- a/ARMeilleure/Instructions/InstName.cs +++ b/ARMeilleure/Instructions/InstName.cs @@ -547,6 +547,7 @@ namespace ARMeilleure.Instructions Vcvt, Vdiv, Vdup, + Veor, Vext, Vld1, Vld2, |